3 Machine-Level ISA, version 1.10
This chapter describes the machine-level operations available in machine-mode (M-mode), which is the highest privilege mode in a RISC-V system. M-mode is the only mandatory privilege mode in a RISC-V hardware implementation. M-mode is used for low-level access to a hardware platform and is the first mode entered at reset. M-mode can also be used to implement features that are too difficult or expensive to implement in hardware directly. The RISC-V machine-level ISA contains a common core that is extended depending on which other privilege levels are supported and other details of the hardware implementation.
3.1 Machine-Level CSRs
In addition to the machine-level CSRs described in this section, M-mode code can access all CSRs at lower privilege levels.
3.1.1 Machine ISA Register misa
The misa CSR is an XLEN-bit WARL read-write register
reporting the ISA supported by the hart. This register must be
readable in any implementation, but a value of zero can be returned to
indicate the misa register has not been implemented, requiring
that CPU capabilities be determined through a separate non-standard
mechanism.
misa).The MXL (Machine XLEN) field encodes the native base integer ISA width
as shown in Table [misabase]. The MXL field may be writable in
implementations that support multiple base ISA widths. The effective
XLEN in M-mode, M-XLEN, is given by the setting of MXL, or has a
fixed value if misa is zero. The MXL field is always set to the
widest supported ISA variant at reset.
| MXL | XLEN |
|---|---|
| 1 | 32 |
| 2 | 64 |
| 3 | 128 |
When MXL is set to a value less than the widest supported XLEN, all operations must ignore source operand register bits above the configured XLEN, and must sign-extend results to fill the entire widest supported XLEN in the destination register.
We require that operations always fill the entire underlying hardware registers with defined values to avoid implementation-defined behavior.
The Extensions field encodes the presence of the standard extensions, with a single bit per letter of the alphabet (bit 0 encodes presence of extension “A” , bit 1 encodes presence of extension “B”, through to bit 25 which encodes “Z”). The “I” bit will be set for RV32I, RV64I, RV128I base ISAs, and the “E” bit will be set for RV32E. The Extension is a WARL field that can contain writable bits where the implementation allows the supported ISA to be modified. At reset, the Extension field should contain the maximal set of supported extensions, and I should be selected over E if both are available.
The “G” bit is used as an escape to allow expansion to a larger space of standard extension names.
G is used to indicate the combination IMAFD, so is redundant in the
misa CSR, hence we reserve the bit to indicate that
additional standard extensions are present.
The “U” and “S” bits will be set if there is support for user and supervisor modes respectively.
The “X” bit will be set if there are any non-standard extensions.
| Bit | Character | Description |
|---|---|---|
| 0 | A | Atomic extension |
| 1 | B | Tentatively reserved for Bit operations extension |
| 2 | C | Compressed extension |
| 3 | D | Double-precision floating-point extension |
| 4 | E | RV32E base ISA |
| 5 | F | Single-precision floating-point extension |
| 6 | G | Additional standard extensions present |
| 7 | H | Reserved |
| 8 | I | RV32I/64I/128I base ISA |
| 9 | J | Tentatively reserved for Dynamically Translated Languages extension |
| 10 | K | Reserved |
| 11 | L | Tentatively reserved for Decimal Floating-Point extension |
| 12 | M | Integer Multiply/Divide extension |
| 13 | N | User-level interrupts supported |
| 14 | O | Reserved |
| 15 | P | Tentatively reserved for Packed-SIMD extension |
| 16 | Q | Quad-precision floating-point extension |
| 17 | R | Reserved |
| 18 | S | Supervisor mode implemented |
| 19 | T | Tentatively reserved for Transactional Memory extension |
| 20 | U | User mode implemented |
| 21 | V | Tentatively reserved for Vector extension |
| 22 | W | Reserved |
| 23 | X | Non-standard extensions present |
| 24 | Y | Reserved |
| 25 | Z | Reserved |
The misa CSR exposes a rudimentary catalog of CPU features
to machine-mode code. More extensive information can be obtained in
machine mode by probing other machine registers, and examining other
ROM storage in the system as part of the boot process.
We require that lower privilege levels execute environment calls instead of reading CPU registers to determine features available at each privilege level. This enables virtualization layers to alter the ISA observed at any level, and supports a much richer command interface without burdening hardware designs.
3.1.2 Machine Vendor ID Register mvendorid
The mvendorid CSR is an XLEN-bit read-only register providing
the JEDEC manufacturer ID of the provider of the core. This register
must be readable in any implementation, but a value of 0 can be
returned to indicate the field is not implemented or that this is a
non-commercial implementation.
mvendorid).JEDEC manufacturer IDs are ordinarily encoded as a sequence of one-byte
continuation codes 0x7f, terminated by a one-byte ID not equal to
0x7f, with an odd parity bit in the most-significant bit of each byte.
mvendorid encodes the number of one-byte continuation
codes in the Bank field, and encodes the final byte in the Offset field,
discarding the parity bit. For example, the JEDEC manufacturer ID
0x7f 0x7f 0x7f 0x7f 0x7f 0x7f 0x7f 0x7f 0x7f 0x7f 0x7f 0x7f 0x8a
(twelve continuation codes followed by 0x8a) would be encoded in the
mvendorid field as 0x60a.
Previously the vendor ID was to be a number allocated by the RISC-V Foundation, but this duplicates the work of JEDEC in maintaining a manufacturer ID standard. At time of writing, registering a manufacturer ID with JEDEC has a one-time cost of $500.
3.1.3 Machine Architecture ID Register marchid
The marchid CSR is an XLEN-bit read-only register encoding the
base microarchitecture of the hart. This register must be readable in
any implementation, but a value of 0 can be returned to indicate the
field is not implemented. The combination of mvendorid and marchid should uniquely identify the type of hart microarchitecture
that is implemented.
marchid).Open-source project architecture IDs are allocated globally by the RISC-V Foundation, and have non-zero architecture IDs with a zero most-significant-bit (MSB). Commercial architecture IDs are allocated by each commercial vendor independently, but must have the MSB set and cannot contain zero in the remaining XLEN-1 bits.
The intent is for the architecture ID to represent the microarchitecture associated with the repo around which development occurs rather than a particular organization. Commercial fabrications of open-source designs should (and might be required by the license to) retain the original architecture ID. This will aid in reducing fragmentation and tool support costs, as well as provide attribution. Open-source architecture IDs should be administered by the Foundation and should only be allocated to released, functioning open-source projects. Commercial architecture IDs can be managed independently by any registered vendor but are required to have IDs disjoint from the open-source architecture IDs (MSB set) to prevent collisions if a vendor wishes to use both closed-source and open-source microarchitectures.
The convention adopted within the following Implementation field can
be used to segregate branches of the same architecture design,
including by organization. The misa register also helps
distinguish different variants of a design, as does the configuration
string if present.
3.1.4 Machine Implementation ID Register mimpid
The mimpid CSR provides a unique encoding of the version of the
processor implementation. This register must be readable in any
implementation, but a value of 0 can be returned to indicate that the
field is not implemented. The Implementation value should reflect the
design of the RISC-V processor itself and not any surrounding system.
mimpid).The format of this field is left to the provider of the architecture source code, but will be often be printed by standard tools as a hexadecimal string without any leading or trailing zeros, so the Implementation value can be left-justified (i.e., filled in from most-significant nibble down) with subfields aligned on nibble boundaries to ease human readability.
3.1.5 Hart ID Register mhartid
The mhartid CSR is an XLEN-bit read-only register
containing the integer ID of the hardware thread running the code.
This register must be readable in any implementation. Hart IDs might
not necessarily be numbered contiguously in a multiprocessor system,
but at least one hart must have a hart ID of zero.
mhartid).In certain cases, we must ensure exactly one hart runs some code (e.g., at reset), and so require one hart to have a known hart ID of zero.
For efficiency, system implementers should aim to reduce the magnitude of the largest hart ID used in a system.
3.1.6 Machine Status Register (mstatus)
The mstatus register is an XLEN-bit read/write register
formatted as shown in Figure 1.6 for RV32 and
Figure 1.7 for RV64 and RV128. The mstatus
register keeps track of and controls the hart’s current operating
state. Restricted views of the mstatus register appear as the
sstatus and ustatus registers in the S-level and U-level
ISAs respectively.
mstatus) for RV32.
mstatus) for RV64 and RV128.3.1.7 Privilege and Global Interrupt-Enable Stack in mstatus register
Interrupt-enable bits, MIE, SIE, and UIE, are provided for each privilege mode. These bits are primarily used to guarantee atomicity with respect to interrupt handlers at the current privilege level. When a hart is executing in privilege mode x, interrupts are enabled when x IE=1. Interrupts for lower privilege modes are always disabled, whereas interrupts for higher privilege modes are always enabled. Higher-privilege-level code can use separate per-interrupt enable bits to disable selected interrupts before ceding control to a lower privilege level.
The xIE bits are located in the low-order bits of mstatus,
allowing them to be atomically set or cleared with a single CSR
instruction.
To support nested traps, each privilege mode x has a two-level stack of interrupt-enable bits and privilege modes. x PIE holds the value of the interrupt-enable bit active prior to the trap, and x PP holds the previous privilege mode. The x PP fields can only hold privilege modes up to x, so MPP is two bits wide, SPP is one bit wide, and UPP is implicitly zero. When a trap is taken from privilege mode y into privilege mode x, x PIE is set to the value of x IE; x IE is set to 0; and x PP is set to y.
For lower privilege modes, any trap (synchronous or asynchronous) is usually taken at a higher privilege mode with interrupts disabled upon entry. The higher-level trap handler will either service the trap and return using the stacked information, or, if not returning immediately to the interrupted context, will save the privilege stack before re-enabling interrupts, so only one entry per stack is required.
The MRET, SRET, or URET instructions are used to return from traps in M-mode, S-mode, or U-mode respectively. When executing an xRET instruction, supposing x PP holds the value y, x IE is set to x PIE; the privilege mode is changed to y; x PIE is set to 1; and x PP is set to U (or M if user-mode is not supported).
When the stack is popped, the lowest-supported privilege mode with interrupts enabled is added to the bottom of stack to help catch errors that cause invalid entries to be popped off the stack.
x PP fields are WLRL fields that need only be able to store supported privilege modes, including x and any implemented privilege mode lower than x.
If the machine provides only U and M modes, then only a single hardware storage bit is required to represent either 00 or 11 in MPP.
User-level interrupts are an optional extension and have been allocated the ISA extension letter N. If user-level interrupts are omitted, the UIE and UPIE bits are hardwired to zero. For all other supported privilege modes x, the x IE and x PIE must not be hardwired.
User-level interrupts are primarily intended to support secure embedded systems with only M-mode and U-mode present, but can also be supported in systems running Unix-like operating systems to support user-level trap handling.
Fields that were previously allocated for H-mode support in mstatus have now been reserved as WPRI fields. To reduce
backwards incompatibility with existing implementations, we did not
compact the register after removing these fields.
3.1.8 Base ISA Control in mstatus Register
For RV64 and RV128 systems, the SXL and UXL fields are WARL fields
that control the value of XLEN for S-mode and U-mode,
respectively. The encoding of these fields is the same as the MXL
field of misa, shown in Table [misabase]. The effective
XLEN in S-mode and U-mode are termed S-XLEN and U-XLEN,
respectively.
For RV32 systems, the SXL and UXL fields do not exist, and S-XLEN = 32 and U-XLEN = 32.
For RV64 and RV128 systems, if S-mode is not supported, then SXL is hardwired to zero. Otherwise, it is a WARL field that encodes the current value of S-XLEN. In particular, the implementation may hardwire SXL so that S-XLEN = M-XLEN.
For RV64 and RV128 systems, if U-mode is not supported, then UXL is hardwired to zero. Otherwise, it is a WARL field that encodes the current value of U-XLEN. In particular, the implementation may hardwire UXL so that U-XLEN = M-XLEN.
Whenever XLEN in any mode is set to a value less than the widest supported XLEN, all operations must ignore source operand register bits above the configured XLEN, and must sign-extend results to fill the entire widest supported XLEN in the destination register.
To reduce hardware complexity, the architecture imposes no checks that lower-privilege modes have XLEN settings less than or equal to the next-higher privilege mode. In practice, such settings would almost always be an error, but machine operation is well-defined even in this case.
3.1.9 Memory Privilege in mstatus Register
The MPRV (Modify PRiVilege) bit modifies the privilege level at which loads and stores execute in all privilege modes. When MPRV=0, translation and protection behave as normal. When MPRV=1, load and store memory addresses are translated and protected as though the current privilege mode were set to MPP. Instruction address-translation and protection are unaffected. MPRV is hardwired to 0 if U-mode is not supported.
The MXR (Make eXecutable Readable) bit modifies the privilege with which loads access virtual memory. When MXR=0, only loads from pages marked readable (R=1 in Figure [sv32pte]) will succeed. When MXR=1, loads from pages marked either readable or executable (R=1 or X=1) will succeed. MXR has no effect when page-based virtual memory is not in effect. MXR is hardwired to 0 if S-mode is not supported.
The MPRV and MXR mechanisms were conceived to improve the efficiency of M-mode routines that emulate missing hardware features, e.g., misaligned loads and stores. MPRV obviates the need to perform address translation in software. MXR allows instruction words to be loaded from pages marked execute-only.
For simplicity, MPRV and MXR are in effect regardless of privilege mode, but in normal use will only be enabled for short sequences in machine mode.
The SUM (permit Supervisor User Memory access) bit modifies the privilege with which S-mode loads, stores, and instruction fetches access virtual memory. When SUM=0, S-mode memory accesses to pages that are accessible by U-mode (U=1 in Figure [sv32pte]) will fault. When SUM=1, these accesses are permitted. SUM has no effect when page-based virtual memory is not in effect. Note that, while SUM is ordinarily ignored when not executing in S-mode, it is in effect when MPRV=1 and MPP=S. SUM is hardwired to 0 if S-mode is not supported.
3.1.10 Virtualization Support in mstatus Register
The TVM (Trap Virtual Memory) bit supports intercepting
supervisor virtual-memory management operations. When TVM=1,
attempts to read or write the satp CSR or execute the SFENCE.VMA
instruction while executing in S-mode will raise an illegal instruction
exception. When TVM=0, these operations are permitted in S-mode.
TVM is hard-wired to 0 when S-mode is not supported.
The TVM mechanism improves virtualization efficiency by permitting guest operating systems to execute in S-mode, rather than classically virtualizing them in U-mode. This approach obviates the need to trap accesses to most S-mode CSRs.
Trapping satp accesses and the SFENCE.VMA instruction provides the
hooks necessary to lazily populate shadow page tables.
The TW (Timeout Wait) bit supports intercepting the WFI instruction (see Section 1.2.3). When TW=0, the WFI instruction is permitted in S-mode. When TW=1, if WFI is executed in S-mode, and it does not complete within an implementation-specific, bounded time limit, the WFI instruction causes an illegal instruction trap. The time limit may always be 0, in which case WFI always causes an illegal instruction trap in S-mode when TW=1. TW is hard-wired to 0 when S-mode is not supported.
Trapping the WFI instruction can trigger a world switch to another guest OS, rather than wastefully idling in the current guest.
The TSR (Trap SRET) bit supports intercepting the supervisor exception return instruction, SRET. When TSR=1, attempts to execute SRET while executing in S-mode will raise an illegal instruction exception. When TSR=0, this operation is permitted in S-mode. TSR is hard-wired to 0 when S-mode is not supported.
Trapping SRET is necessary to emulate the Augmented Virtualization mechanism (see Chapter [hypervisor]) on implementations that do not provide it.
3.1.11 Extension Context Status in mstatus Register
Supporting substantial extensions is one of the primary goals of RISC-V, and hence we define a standard interface to allow unchanged privileged-mode code, particularly a supervisor-level OS, to support arbitrary user-mode state extensions.
To date, there are no standard extensions that define additional state beyond the floating-point CSR and data registers.
The FS[1:0] read/write field and the XS[1:0] read-only field are used
to reduce the cost of context save and restore by setting and tracking
the current state of the floating-point unit and any other user-mode
extensions respectively. The FS field encodes the status of the
floating-point unit, including the CSR fcsr and floating-point
data registers f0–f31, while the XS field encodes the
status of additional user-mode extensions and associated state.
These fields can be checked by a context switch routine to quickly
determine whether a state save or restore is required. If a save or
restore is required, additional instructions and CSRs are typically
required to effect and optimize the process.
The design anticipates that most context switches will not need to save/restore state in either or both of the floating-point unit or other extensions, so provides a fast check via the SD bit.
The FS and XS fields use the same status encoding as shown in Table [fsxsencoding], with the four possible status values being Off, Initial, Clean, and Dirty.
| Status | FS Meaning | XS Meaning |
|---|---|---|
| 0 | Off | All off |
| 1 | Initial | None dirty or clean, some on |
| 2 | Clean | None dirty, some clean |
| 3 | Dirty | Some dirty |
In systems that do not implement S-mode and do not have a floating-point unit, the FS field is hardwired to zero.
In systems without additional user extensions requiring new state, the
XS field is hardwired to zero. Every additional extension with state
adds a local field to mstatus encoding the equivalent of the XS states.
The XS field represents a summary of all
extensions’ status as shown in Table [fsxsencoding].
The XS field effectively reports the maximum status value across all user-extension status fields, though individual extensions can use a different encoding than XS.
The SD bit is a read-only bit that summarizes whether either the FS field or XS field signals the presence of some dirty state that will require saving extended user context to memory. If both XS and FS are hardwired to zero, then SD is also always zero.
When an extension’s status is set to Off, any instruction that attempts to read or write the corresponding state will cause an exception. When the status is Initial, the corresponding state should have an initial constant value. When the status is Clean, the corresponding state is potentially different from the initial value, but matches the last value stored on a context swap. When the status is Dirty, the corresponding state has potentially been modified since the last context save.
During a context save, the responsible privileged code need only write out the corresponding state if its status is Dirty, and can then reset the extension’s status to Clean. During a context restore, the context need only be loaded from memory if the status is Clean (it should never be Dirty at restore). If the status is Initial, the context must be set to an initial constant value on context restore to avoid a security hole, but this can be done without accessing memory. For example, the floating-point registers can all be initialized to the immediate value 0.
The FS and XS fields are read by the privileged code before saving the context. The FS field is set directly by privileged code when resuming a user context, while the XS field is set indirectly by writing to the status register of the individual extensions. The status fields will also be updated during execution of instructions, regardless of privilege mode.
Extensions to the user-mode ISA often include additional user-mode state, and this state can be considerably larger than the base integer registers. The extensions might only be used for some applications, or might only be needed for short phases within a single application. To improve performance, the user-mode extension can define additional instructions to allow user-mode software to return the unit to an initial state or even to turn off the unit.
For example, a coprocessor might require to be configured before use and can be “unconfigured” after use. The unconfigured state would be represented as the Initial state for context save. If the same application remains running between the unconfigure and the next configure (which would set status to Dirty), there is no need to actually reinitialize the state at the unconfigure instruction, as all state is local to the user process, i.e., the Initial state may only cause the coprocessor state to be initialized to a constant value at context restore, not at every unconfigure.
Executing a user-mode instruction to disable a unit and place it into the Off state will cause an illegal instruction exception to be raised if any subsequent instruction tries to use the unit before it is turned back on. A user-mode instruction to turn a unit on must also ensure the unit’s state is properly initialized, as the unit might have been used by another context meantime.
Changing the setting of FS has no effect on the contents of the floating-point register state. In particular, setting FS=Off does not destroy the state, nor does setting FS=Initial clear the contents. Other extensions might not preserve state when set to Off.
Table 1.8 shows all the possible state transitions for the FS or XS status bits. Note that the standard floating-point extensions do not support user-mode unconfigure or disable/enable instructions.
Standard privileged instructions to initialize, save, and restore extension state are provided to insulate privileged code from details of the added extension state by treating the state as an opaque object.
Many coprocessor extensions are only used in limited contexts that allows software to safely unconfigure or even disable units when done. This reduces the context-switch overhead of large stateful coprocessors.
We separate out floating-point state from other extension state, as when a floating-point unit is present the floating-point registers are part of the standard calling convention, and so user-mode software cannot know when it is safe to disable the floating-point unit.
The XS field provides a summary of all added extension state, but additional microarchitectural bits might be maintained in the extension to further reduce context save and restore overhead.
The SD bit is read-only and is set when either the FS or XS bits encode a Dirty state (i.e., SD=((FS==11) OR (XS==11))). This allows privileged code to quickly determine when no additional context save is required beyond the integer register set and PC.
The floating-point unit state is always initialized, saved, and
restored using standard instructions (F, D, and/or Q), and privileged
code must be aware of FLEN to determine the appropriate space to
reserve for each f register.
In a supervisor-level OS, any additional user-mode state should be initialized, saved, and restored using SBI calls that treats the additional context as an opaque object of a fixed maximum size. The implementation of the SBI initialize, save, and restore calls might require additional implementation-dependent privileged instructions to initialize, save, and restore microarchitectural state inside a coprocessor.
All privileged modes share a single copy of the FS and XS bits. In a system with more than one privileged mode, supervisor mode would normally use the FS and XS bits directly to record the status with respect to the supervisor-level saved context. Other more-privileged active modes must be more conservative in saving and restoring the extension state in their corresponding version of the context.
In any reasonable use case, the number of context switches between user and supervisor level should far outweigh the number of context switches to other privilege levels. Note that coprocessors should not require their context to be saved and restored to service asynchronous interrupts, unless the interrupt results in a user-level context swap.
3.1.12 Machine Trap-Vector Base-Address Register (mtvec)
The mtvec register is an XLEN-bit read/write register that holds
trap vector configuration, consisting of a vector base address (BASE) and a
vector mode (MODE).
mtvec).The mtvec register must always be implemented, but can contain
a hardwired read-only value. If mtvec is writable, the set of values
the register may hold can vary by implementation. The value in the BASE field
must always be aligned on a 4-byte boundary, and the MODE setting may impose
additional alignment constraints on the value in the BASE field.
We allow for considerable flexibility in implementation of the trap vector base address. On the one hand, we do not wish to burden low-end implementations with a large number of state bits, but on the other hand, we wish to allow flexibility for larger systems.
| Value | Name | Description |
|---|---|---|
| 0 | Direct | All exceptions set pc to BASE. |
| 1 | Vectored | Asynchronous interrupts set pc to BASE+4×cause. |
| ≥2 | — | Reserved |
The encoding of the MODE field is shown in Table [mtvec-mode]. When
MODE=Direct, all traps into machine mode cause the pc to be set to the
address in the BASE field. When MODE=Vectored, all synchronous exceptions
into machine mode cause the pc to be set to the address in the BASE
field, whereas interrupts cause the pc to be set to the address in
the BASE field plus four times the interrupt cause number. For example,
a machine-mode timer interrupt (see Table [mcauses]) causes the pc
to be set to BASE+0x1c.
Setting MODE=Vectored may impose an additional alignment constraint on BASE,
requiring up to 4 × XLEN-byte alignment.
When vectored interrupts are enabled, interrupt cause 0, which corresponds to user-mode software interrupts, are vectored to the same location as synchronous exceptions. This ambiguity does not arise in practice, since user-mode software interrupts are either disabled or delegated to a less-privileged mode.
Reset and NMI vector locations are given in a platform specification.
3.1.13 Machine Trap Delegation Registers (medeleg and mideleg)
By default, all traps at any privilege level are handled in machine
mode, though a machine-mode handler can redirect traps back to the
appropriate level with the MRET instruction (Section 1.2.2).
To increase performance, implementations can provide individual
read/write bits within medeleg and mideleg to indicate
that certain exceptions and interrupts should be processed directly by
a lower privilege level. The machine exception delegation register
(medeleg) and machine interrupt delegation register ( mideleg) are XLEN-bit read/write registers.
In systems with all three privilege modes (M/S/U), setting a bit in
medeleg or mideleg will delegate the corresponding trap in
S-mode or U-mode to the S-mode trap handler. If U-mode traps are
supported, S-mode may in turn set corresponding bits in the sedeleg and sideleg registers to delegate traps that occur in
U-mode to the U-mode trap handler.
In systems with two privilege modes (M/U) and support for U-mode
traps, setting a bit in medeleg or mideleg will
delegate the corresponding trap in U-mode to the U-mode trap handler.
In systems with only M-mode, or with both M-mode and U-mode but
without U-mode trap support, the medeleg and mideleg
registers should not exist.
In versions 1.9.1 and earlier , these registers existed but were
hardwired to zero in M-mode only, or M/U without N systems. There
is no reason to require they return zero in those cases, as the misa register indicates whether they exist.
When a trap is delegated to a less-privileged mode x, the
x cause register is written with the trap cause; the
x epc register is written with the virtual address of
the instruction that took the trap; the x PP field
of mstatus is written with the active privilege mode at the time of
the trap; the x PIE field of mstatus is written with the
value of the active interrupt-enable bit at the time of the trap; and
the x IE field of mstatus is cleared. The mcause and
mepc registers and the MPP and MPIE fields of mstatus are
not written.
An implementation shall not hardwire any delegation bits to one, i.e.,
any trap that can be delegated must support not being delegated. An
implementation can choose to subset the delegatable traps, with the
supported delegatable bits found by writing one to every bit location,
then reading back the value in medeleg or mideleg to see
which bit positions hold a one.
Traps never transition from a more-privileged mode to a less-privileged mode. For example, if M-mode has delegated illegal instruction traps to S-mode, and M-mode software later executes an illegal instruction, the trap is taken in M-mode, rather than being delegated to S-mode. By contrast, traps may be taken horizontally. Using the same example, if M-mode has delegated illegal instruction traps to S-mode, and S-mode software later executes an illegal instruction, the trap is taken in S-mode.
medeleg.medeleg has a bit position allocated for every synchronous exception
shown in Table [mcauses], with the index of the bit position equal to the
value returned in the mcause register (i.e., setting bit 8 allows
user-mode environment calls to be delegated to a lower-privilege trap
handler).
mideleg.mideleg holds trap delegation bits for individual interrupts, with the
layout of bits matching those in the mip register (i.e., STIP interrupt
delegation control is located in bit 5).
Some exceptions cannot occur at less privileged modes, and corresponding
x edeleg bits should be hardwired to zero. In particular,
medeleg[11] and sedeleg[11:9] are all hardwired to zero.
3.1.14 Machine Interrupt Registers (mip and mie)
The mip register is an XLEN-bit read/write register containing
information on pending interrupts, while mie is the
corresponding XLEN-bit read/write register containing interrupt enable
bits. Only the bits corresponding to lower-privilege software
interrupts (USIP, SSIP), timer interrupts (UTIP, STIP),
and external interrupts (UEIP, SEIP) in mip
are writable through this CSR address; the remaining bits are
read-only.
Restricted views of the mip and mie registers appear as
the sip/sie, and uip/uie registers in
S-mode and U-mode respectively. If an interrupt is delegated to
privilege mode x by setting a bit in the mideleg register,
it becomes visible in the x ip register and is maskable
using the x ie register. Otherwise, the corresponding
bits in x ip and x ie appear to be hardwired
to zero.
mip).
mie).The MTIP, STIP, UTIP bits correspond to timer interrupt-pending bits for machine, supervisor, and user timer interrupts, respectively. The MTIP bit is read-only and is cleared by writing to the memory-mapped machine-mode timer compare register. The UTIP and STIP bits may be written by M-mode software to deliver timer interrupts to lower privilege levels. User and supervisor software may clear the UTIP and STIP bits with calls to the AEE and SEE respectively.
There is a separate timer interrupt-enable bit, named MTIE, STIE, and UTIE for M-mode, S-mode, and U-mode timer interrupts respectively.
Each lower privilege level has a separate software interrupt-pending bit (SSIP, USIP), which can be both read and written by CSR accesses from code running on the local hart at the associated or any higher privilege level. The machine-level MSIP bits are written by accesses to memory-mapped control registers, which are used by remote harts to provide machine-mode interprocessor interrupts. Interprocessor interrupts for lower privilege levels are implemented through ABI and SBI calls to the AEE or SEE respectively, which might ultimately result in a machine-mode write to the receiving hart’s MSIP bit. A hart can write its own MSIP bit using the same memory-mapped control register.
We only allow a hart to directly write its own SSIP or USIP bits when running in the appropriate mode, as other harts might be virtualized and possibly descheduled by higher privilege levels. We rely on ABI and SBI calls to provide interprocessor interrupts for this reason. Machine-mode harts are not virtualized and can directly interrupt other harts by setting their MSIP bits, typically using uncached I/O writes to memory-mapped control registers depending on the platform specification.
The MEIP field in mip is a read-only bit that indicates a machine-mode
external interrupt is pending. MEIP is set and cleared by a platform-specific
interrupt controller, such as the standard platform-level interrupt controller
specified in Chapter [plic]. The MEIE field in mie enables machine
external interrupts when set.
The SEIP field in mip contains a single read-write bit. SEIP
may be written by M-mode software to indicate to S-mode that an
external interrupt is pending. Additionally, the platform-level
interrupt controller may generate supervisor-level external interrupts. The
logical-OR of the software-writeable bit and the signal from the
external interrupt controller is used to generate external interrupts
to the supervisor. When the SEIP bit is read with a CSRRW, CSRRS, or
CSRRC instruction, the value returned in the rd destination
register contains the logical-OR of the software-writable bit and the
interrupt signal from the interrupt controller. However, the value
used in the read-modify-write sequence of a CSRRS or CSRRC instruction
is only the software-writable SEIP bit, ignoring the interrupt value
from the external interrupt controller.
The SEIP field behavior is designed to allow a higher privilege layer to mimic external interrupts cleanly, without losing any real external interrupts. The behavior of the CSR instructions is slightly modified from regular CSR accesses as a result.
The UEIP field in mip provides user-mode external interrupts when the
N extension for user-mode interrupts is implemented. It is defined
analogously to SEIP.
The MEIE, SEIE, and UEIE fields in the mie CSR enable M-mode external
interrupts, S-mode external interrupts, and U-mode external interrupts,
respectively.
The non-maskable interrupt is not made visible via the mip
register as its presence is implicitly known when executing the NMI
trap handler.
For all the various interrupt types (software, timer, and external),
if a privilege level is not supported, the associated pending and
interrupt-enable bits are hardwired to zero in the mip and mie registers respectively. Hence, these are all effectively
WARL fields.
Implementations can add additional platform-specific machine-level interrupt sources to the high bits of these registers, though the expectation is that most external interrupts will be routed through the platform interrupt controller and be delivered via MEIP.
An interrupt i will be taken if bit i is set in both mip and mie, and if interrupts are globally enabled. By
default, M-mode interrupts are globally enabled if the hart’s current
privilege mode is less than M, or if the current privilege mode is M
and the MIE bit in the mstatus register is set. If bit i
in mideleg is set, however, interrupts are considered to be
globally enabled if the hart’s current privilege mode equals the
delegated privilege mode (S or U) and that mode’s interrupt enable
bit (SIE or UIE in mstatus) is set, or if the current
privilege mode is less than the delegated privilege mode.
Multiple simultaneous interrupts and traps at the same privilege level are handled in the following decreasing priority order: external interrupts, software interrupts, timer interrupts, then finally any synchronous traps.
3.1.15 Machine Timer Registers (mtime and mtimecmp)
Platforms provide a real-time counter, exposed as a memory-mapped
machine-mode register, mtime. mtime must run at constant
frequency, and the platform must provide a mechanism for determining
the timebase of mtime.
The mtime register has a 64-bit precision on all RV32, RV64, and
RV128 systems. Platforms provide a 64-bit memory-mapped machine-mode
timer compare register (mtimecmp), which causes a timer
interrupt to be posted when the mtime register contains a value
greater than or equal to the value in the mtimecmp register.
The interrupt remains posted until it is cleared by writing the mtimecmp register. The interrupt will only be taken if interrupts
are enabled and the MTIE bit is set in the mie register.
The timer facility is defined to use wall-clock time rather than a cycle counter to support modern processors that run with a highly variable clock frequency to save energy through dynamic voltage and frequency scaling.
Accurate real-time clocks (RTCs) are relatively expensive to provide
(requiring a crystal or MEMS oscillator) and have to run even when the
rest of system is powered down, and so there is usually only one in a
system located in a different frequency/voltage domain from the
processors. Hence, the RTC must be shared by all the harts in a
system and accesses to the RTC will potentially incur the penalty of a
voltage-level-shifter and clock-domain crossing. It is thus more
natural to expose mtime as a memory-mapped register than as a CSR.
Lower privilege levels do not have their own timecmp registers.
Instead, machine-mode software can implement any number of virtual timers on
a hart by multiplexing the next timer interrupt into the mtimecmp
register.
Simple fixed-frequency systems can use a single clock for both cycle counting and wall-clock time.
In RV32, memory-mapped writes to mtimecmp modify only one 32-bit
part of the register. The following code sequence sets a 64-bit mtimecmp value without spuriously generating a timer interrupt due
to the intermediate value of the comparand:
3.1.16 Hardware Performance Monitor
M-mode includes a basic hardware performance monitoring facility. The mcycle CSR holds a count of the number of cycles the hart has executed since
some arbitrary time in the past. The minstret CSR holds a count of the
number of instructions the hart has retired since some arbitrary time in the
past. The mcycle and minstret registers have 64-bit precision on
all RV32, RV64, and RV128 systems.
The hardware performance monitor includes 29 additional event counters, mhpmcounter3–mhpmcounter31. The event selector CSRs, mhpmevent3–mhpmevent31, are WARL registers that control which event
causes the corresponding counter to increment. The meaning of these events is
defined by the platform, but event 0 is reserved to mean “no event.”
All counters should be implemented, but a legal implementation is to hard-wire
both the counter and its corresponding event selector to 0.
All of these counters have 64-bit precision on RV32, RV64, and RV128.
On RV32 only, reads of the mcycle, minstret, and mhpmcountern CSRs return the low 32 bits, while reads of the mcycleh, minstreth, and mhpmcounternh CSRs return bits
63–32 of the corresponding counter.
On RV128 systems, the 64-bit values in mcycle, minstret, and
mhpmcountern are sign-extended to 128-bits when read.
On RV128 systems, both signed and unsigned 64-bit values are held in a canonical form with bit 63 repeated in all higher bit positions. The counters are 64-bit values even in RV128, and so the counter CSR reads preserve the sign-extension invariant. Implementations may choose to implement fewer bits of the counters, provided software would be unlikely to experience wraparound (e.g., 263 instructions executed) and thereby avoid having to actually implement the sign-extension circuitry.
3.1.17 Counter-Enable Registers ([m|h|s]counteren)
mcounteren and scounteren).The counter-enable registers mcounteren and scounteren
control the availability of the hardware performance monitoring
counters to the next-lowest privileged mode.
When the CY, TM, IR, or HPMn bit in the mcounteren
register is clear, attempts to read the cycle, time, instret, or hpmcountern register while executing in
S-mode or U-mode will cause an illegal instruction exception. When
one of these bits is set, access to the corresponding register is
permitted in the next implemented privilege mode (S-mode if
implemented, otherwise U-mode).
If S-mode is implemented, the same bit positions in the scounteren
register analogously control access to these registers while executing
in U-mode. If S-mode is permitted to access a counter register and the
corresponding bit is set in scounteren, then U-mode is also permitted
to access that register.
Registers mcounteren and scounteren are WARL registers
that must be implemented if U-mode and S-mode are implemented,
Any of the bits may contain
a hardwired value of zero, indicating reads to the corresponding counter will
cause an exception when executing in a less-privileged mode.
The counter-enable bits support two common use cases with minimal hardware. For systems that do not need high-performance timers and counters, machine-mode software can trap accesses and implement all features in software. For systems that need high-performance timers and counters but are not concerned with obfuscating the underlying hardware counters, the counters can be directly exposed to lower privilege modes.
The cycle, instret, and hpmcountern CSRs are
read-only shadows of mcycle, minstret, and mhpmcounter n, respectively. The time CSR is a read-only shadow of the
memory-mapped mtime register.
Implementations can convert reads of the time CSR into loads to
the memory-mapped mtime register, or hard-wire the TM bits in
mxcounteren to 0
and emulate this functionality in M-mode software.
3.1.18 Machine Scratch Register (mscratch)
The mscratch register is an XLEN-bit read/write register
dedicated for use by machine mode. Typically, it is used to hold a
pointer to a machine-mode hart-local context space and swapped with a
user register upon entry to an M-mode trap handler.
The MIPS ISA allocated two user registers (k0/k1) for use
by the operating system. Although the MIPS scheme provides a fast and
simple implementation, it also reduces available user registers, and
does not scale to further privilege levels, or nested traps. It can
also require both registers are cleared before returning to user level
to avoid a potential security hole and to provide deterministic
debugging behavior.
The RISC-V user ISA was designed to support many possible privileged
system environments and so we did not want to infect the user-level
ISA with any OS-dependent features. The RISC-V CSR swap instructions
can quickly save/restore values to the mscratch register.
Unlike the MIPS design, the OS can rely on holding a value in the mscratch register while the user context is running.
3.1.19 Machine Exception Program Counter (mepc)
mepc is an XLEN-bit read/write register formatted as shown in
Figure 1.17. The low bit of mepc (mepc[0]) is
always zero. On implementations that do not support instruction-set
extensions with 16-bit instruction alignment, the two low bits ( mepc[1:0]) are always zero.
The mepc register can never hold a PC value that would cause an
instruction-address-misaligned exception.
mepc is a WARL register that must be able to hold all valid physical
and virtual addresses. It need not be capable of holding all possible invalid
addresses. Implementations may convert some invalid address patterns into
other invalid addresses prior to writing them to mepc.
When a trap is taken into M-mode, mepc is written with the virtual
address of the instruction that encountered the exception. Otherwise,
mepc is never written by the implementation, though it may be
explicitly written by software.
3.1.20 Machine Cause Register (mcause)
The mcause register is an XLEN-bit read-write register formatted as
shown in Figure 1.18. When a trap is taken into M-mode, mcause is written with a code indicating the event that caused the trap.
Otherwise, mcause is never written by the implementation, though it may be
explicitly written by software.
The Interrupt bit in the mcause register is set if the
trap was caused by an interrupt. The Exception Code field
contains a code identifying the last exception. Table [mcauses]
lists the possible machine-level exception codes. The Exception Code
is an WLRL field, so is only guaranteed to hold supported exception
codes.
mcause.| Interrupt | Exception Code | Description | |
|---|---|---|---|
| 1 | 0 | User software interrupt | |
| 1 | 1 | Supervisor software interrupt | |
| 1 | 2 | Reserved | |
| 1 | 3 | Machine software interrupt | |
| 1 | 4 | User timer interrupt | |
| 1 | 5 | Supervisor timer interrupt | |
| 1 | 6 | Reserved | |
| 1 | 7 | Machine timer interrupt | |
| 1 | 8 | User external interrupt | |
| 1 | 9 | Supervisor external interrupt | |
| 1 | 10 | Reserved | |
| 1 | 11 | Machine external interrupt | |
| 1 | ≥12 | Reserved | |
| 0 | 0 | Instruction address misaligned | |
| 0 | 1 | Instruction access fault | |
| 0 | 2 | Illegal instruction | |
| 0 | 3 | Breakpoint | |
| 0 | 4 | Load address misaligned | |
| 0 | 5 | Load access fault | |
| 0 | 6 | Store/AMO address misaligned | |
| 0 | 7 | Store/AMO access fault | |
| 0 | 8 | Environment call from U-mode | |
| 0 | 9 | Environment call from S-mode | |
| 0 | 10 | Reserved | |
| 0 | 11 | Environment call from M-mode | |
| 0 | 12 | Instruction page fault | |
| 0 | 13 | Load page fault | |
| 0 | 14 | Reserved | |
| 0 | 15 | Store/AMO page fault | |
| 0 | ≥16 | Reserved |
We do not distinguish privileged instruction exceptions from illegal opcode exceptions. This simplifies the architecture and also hides details of which higher-privilege instructions are supported by an implementation. The privilege level servicing the trap can implement a policy on whether these need to be distinguished, and if so, whether a given opcode should be treated as illegal or privileged.
Interrupts can be separated from other traps with a single branch on the sign of
the mcause register value. A shift left can remove the
interrupt bit and scale the exception codes to index into a trap
vector table.
3.1.21 Machine Trap Value (mtval) Register
The mtval register is an XLEN-bit read-write register formatted as shown
in Figure 1.19. When a trap is taken into M-mode, mtval is
written with exception-specific information to assist software in handling the
trap. Otherwise, mtval is never written by the implementation, though
it may be explicitly written by software.
When a hardware
breakpoint is triggered, or an instruction-fetch, load, or store
address-misaligned, access, or page-fault exception occurs, mtval is
written with the faulting effective address. On an illegal instruction trap,
mtval is written with the first XLEN bits of the faulting
instruction as described below. For other exceptions, mtval is
set to zero, but a future standard may redefine mtval’s setting for
other exceptions.
The mtval register replaces the mbadaddr register in
the previous specification. In addition to providing bad addresses,
the register can now provide the bad instruction that triggered an
illegal instruction trap (and may in future be used to return other
information). Returning the instruction bits accelerates instruction emulation and also
removes some races that might be present when trying to emulate
illegal instructions.
When page-based virtual memory is enabled, mtval is written with
the faulting virtual address, even for physical-memory access exceptions.
This design reduces datapath cost for most implementations, particularly
those with hardware page-table walkers.
For instruction-fetch access faults on RISC-V systems with
variable-length instructions, mtval will contain a pointer to
the portion of the instruction that caused the fault while mepc
will point to the beginning of the instruction.
The mtval register can optionally also be used to return the
faulting instruction bits on an illegal instruction exception ( mepc points to the faulting instruction in memory).
If this feature is not provided, then mtval is set to zero on
an illegal instruction fault.
If the feature is provided, after an illegal instruction trap, mtval will contain the entire faulting instruction provided the
instruction is no longer than XLEN bits. If the instruction is less
than XLEN bits long, the upper bits of mtval are cleared to
zero. If the instruction is more than XLEN bits long, mtval
will contain the first XLEN bits of the instruction.
Capturing the faulting instruction in mtval reduces the
overhead of instruction emulation, potentially avoiding several
partial instruction loads if the instruction is misaligned, and
likely data cache misses or slow uncached accesses when loads are
used to fetch the instruction into a data register. There is also a
problem of atomicity if another agent is manipulating the
instruction memory, as might occur in a dynamic translation system.
A requirement is that the entire instruction (or at least the first
XLEN bits) are fetched into mtval before taking the trap.
This should not constrain implementations, which would typically
fetch the entire instruction before attempting to decode the
instruction, and avoids complicating software handlers.
A value of zero in mtval signifies either that the feature is
not supported, or an illegal zero instruction was fetched. A load
from the instruction memory pointed to by mepc can be used to
distinguish these two cases (or alternatively, the system
configuration information can be interrogated to install the
appropriate trap handling before runtime).
mtval is a WARL register that must be able to hold all valid physical
and virtual addresses and the value 0. It need not be capable of holding all
possible invalid addresses. Implementations may convert some invalid address
patterns into other invalid addresses prior to writing them to mtval.
If the feature to return the faulting instruction bits is implemented, mtval must also be able to hold all values less than 2N, where N is the
smaller of XLEN and the width of the longest supported instruction.
3.2 Machine-Mode Privileged Instructions
3.2.1 Environment Call and Breakpoint
The ECALL instruction is used to make a request to the supporting execution environment. When executed in U-mode, S-mode, or M-mode, it generates an environment-call-from-U-mode exception, environment-call-from-S-mode exception, or environment-call-from-M-mode exception, respectively, and performs no other operation.
ECALL generates a different exception for each originating privilege mode so that environment call exceptions can be selectively delegated. A typical use case for Unix-like operating systems is to delegate to S-mode the environment-call-from-U-mode exception but not the others.
The EBREAK instruction is used by debuggers to cause control to be transferred back to a debugging environment. It generates a breakpoint exception and performs no other operation.
As described in the “C” Standard Extension for Compressed Instructions in Volume I of this manual, the C.EBREAK instruction performs the same operation as the EBREAK instruction.
ECALL and EBREAK cause the receiving privilege mode’s epc register
to be set to the address of the ECALL or EBREAK instruction itself, not
the address of the following instruction.
3.2.2 Trap-Return Instructions
Instructions to return from trap are encoded under the PRIV minor opcode.
To return after handling a trap, there are separate trap return
instructions per privilege level: MRET, SRET, and URET. MRET is
always provided, while SRET must be provided if supervisor mode is
supported. URET is only provided if user-mode traps are supported.
An x RET instruction can be executed in privilege mode x
or higher, where executing a lower-privilege x RET instruction
will pop the relevant lower-privilege interrupt enable and privilege
mode stack. In addition to manipulating the privilege stack as
described in Section 1.1.7, x RET sets the pc
to the value stored in the x epc register.
Previously, there was only a single ERET instruction (which was also earlier known as SRET). To support the addition of user-level interrupts, we needed to add a separate URET instruction to continue to allow classic virtualization of OS code using the ERET instruction. It then became more orthogonal to support a different xRET instruction per privilege level.
3.2.3 Wait for Interrupt
The Wait for Interrupt instruction (WFI) provides a hint to the implementation that the current hart can be stalled until an interrupt might need servicing. Execution of the WFI instruction can also be used to inform the hardware platform that suitable interrupts should preferentially be routed to this hart. WFI is available in all of the supported S and M privilege modes, and optionally available to U-mode for implementations that support U-mode interrupts.
If an enabled interrupt is present or later becomes present while the
hart is stalled, the interrupt exception will be taken on the
following instruction, i.e., execution resumes in the trap handler and
mepc = pc + 4.
The following instruction takes the interrupt exception and trap, so that a simple return from the trap handler will execute code after the WFI instruction.
The WFI instruction is just a hint, and a legal implementation is to implement WFI as a NOP.
If the implementation does not stall the hart on execution of the instruction, then the interrupt will be taken on some instruction in the idle loop containing the WFI, and on a simple return from the handler, the idle loop will resume execution.
We have removed the earlier requirement that implementations ignore the rs1 and rd fields, so non-zero values in these fields should now raise illegal instruction exceptions.
The WFI instruction can also be executed when interrupts are disabled. The
operation of WFI must be unaffected by the global interrupt bits in mstatus (MIE/SIE/UIE) and the delegation registers [m|s|u]ideleg
(i.e., the hart must resume if a locally enabled interrupt becomes pending,
even if it has been delegated to a less-privileged mode), but should honor the
individual interrupt enables (e.g, MTIE) (i.e., implementations should
avoid resuming the hart if the interrupt is pending but not
individually enabled). WFI is also required to resume execution for
locally enabled interrupts pending at any privilege level, regardless
of the global interrupt enable at each privilege level.
If the event that causes the hart to resume execution does not cause
an interrupt to be taken, execution will resume at pc + 4, and
software must determine what action to take, including looping back to
repeat the WFI if there was no actionable event.
By allowing wakeup when interrupts are disabled, an alternate entry point to an interrupt handler can be called that does not require saving the current context, as the current context can be saved or discarded before the WFI is executed.
As implementations are free to implement WFI as a NOP, software must
explicitly check for any relevant pending but disabled interrupts in
the code following an WFI, and should loop back to the WFI if no
suitable interrupt was detected. The mip, sip,
or uip registers can be interrogated to determine the presence
of any interrupt in machine, supervisor, or user mode
respectively.
The operation of WFI is unaffected by the delegation register settings.
WFI is defined so that an implementation can trap into a higher privilege mode, either immediately on encountering the WFI or after some interval to initiate a machine-mode transition to a lower power state, for example.
The same “wait-for-event” template might be used for possible future extensions that wait on memory locations changing, or message arrival.
3.3 Reset
Upon reset, a hart’s privilege mode is set to M. The mstatus fields MIE
and MPRV are reset to 0. The pc is
set to an implementation-defined reset vector. The mcause register is
set to a value indicating the cause of the reset. All other hart state is
undefined.
The mcause values after reset have implementation-specific
interpretation, but the value 0 should be returned on implementations
that do not distinguish different reset conditions. Implementations
that distinguish different reset conditions should only use 0 to
indicate the most complete reset (e.g., hard reset).
Some designs may have multiple causes of reset (e.g., power-on reset, external hard reset, brownout detected, watchdog timer elapse, sleep-mode wakeup), which machine-mode software and debuggers may wish to distinguish.
mcause reset values may alias mcause values following
synchronous exceptions. There is no ambiguity in this overlap, since
on reset the pc is set to a different value than on other traps.
3.4 Non-Maskable Interrupts
Non-maskable interrupts (NMIs) are only used for hardware error
conditions, and cause an immediate jump to an implementation-defined
NMI vector running in M-mode regardless of the state of a hart’s
interrupt enable bits. The mepc register is written with the
address of the next instruction to be executed at the time the NMI was
taken, and mcause is set to a value indicating the source of the
NMI. The NMI can thus overwrite state in an active machine-mode
interrupt handler.
The values written to mcause on an NMI are
implementation-defined, but a value of 0 is reserved to mean “unknown
cause” and implementations that do not distinguish sources of NMIs
via the mcause register should return 0.
Unlike resets, NMIs do not reset processor state, enabling diagnosis, reporting, and possible containment of the hardware error.
3.5 Physical Memory Attributes
The physical memory map for a complete system includes various address ranges, some corresponding to memory regions, some to memory-mapped control registers, and some to empty holes in the address space. Some memory regions might not support reads, writes, or execution; some might not support subword or subblock accesses; some might not support atomic operations; and some might not support cache coherence or might have different memory models. Similarly, memory-mapped control registers vary in their supported access widths, support for atomic operations, and whether read and write accesses have associated side effects. In RISC-V systems, these properties and capabilities of each region of the machine’s physical address space are termed physical memory attributes (PMAs). This section describes RISC-V PMA terminology and how RISC-V systems implement and check PMAs.
PMAs are inherent properties of the underlying hardware and rarely change during system operation. Unlike physical memory protection values described in Section 1.6, PMAs do not vary by execution context. The PMAs of some memory regions are fixed at chip design time—for example, for an on-chip ROM. Others are fixed at board design time, depending, for example, on which other chips are connected to off-chip buses. Off-chip buses might also support devices that could be changed on every power cycle (cold pluggable) or dynamically while the system is running (hot pluggable). Some devices might be configurable at run time to support different uses that imply different PMAs—for example, an on-chip scratchpad RAM might be cached privately by one core in one end-application, or accessed as a shared non-cached memory in another end-application.
Most systems will require that at least some PMAs are dynamically checked in hardware later in the execution pipeline after the physical address is known, as some operations will not be supported at all physical memory addresses, and some operations require knowing the current setting of a configurable PMA attribute. While many other systems specify some PMAs in the virtual memory page tables and use the TLB to inform the pipeline of these properties, this approach injects platform-specific information into a virtualized layer and can cause system errors unless attributes are correctly initialized in each page-table entry for each physical memory region. In addition, the available page sizes might not be optimal for specifying attributes in the physical memory space, leading to address-space fragmentation and inefficient use of expensive TLB entries.
For RISC-V, we separate out specification and checking of PMAs into a separate hardware structure, the PMA checker. In many cases, the attributes are known at system design time for each physical address region, and can be hardwired into the PMA checker. Where the attributes are run-time configurable, platform-specific memory-mapped control registers can be provided to specify these attributes at a granularity appropriate to each region on the platform (e.g., for an on-chip SRAM that can be flexibly divided between cacheable and uncacheable uses). PMAs are checked for any access to physical memory, including accesses that have undergone virtual to physical memory translation. To aid in system debugging, we strongly recommend that, where possible, RISC-V processors precisely trap physical memory accesses that fail PMA checks. Precisely trapped PMA violations manifest as load, store, or instruction-fetch access exceptions, distinct from virtual-memory page-fault exceptions. Precise PMA traps might not always be possible, for example, when probing a legacy bus architecture that uses access failures as part of the discovery mechanism. In this case, error responses from slave devices will be reported as imprecise bus-error interrupts.
PMAs must also be readable by software to correctly access certain devices or to correctly configure other hardware components that access memory, such as DMA engines. As PMAs are tightly tied to a given physical platform’s organization, many details are inherently platform-specific, as is the means by which software can learn the PMA values for a platform. The configuration string (Chapter [cfgstr]) can encode PMAs for on-chip devices and might also describe on-chip controllers for off-chip buses that can be dynamically interrogated to discover attached device PMAs. Some devices, particularly legacy buses, do not support discovery of PMAs and so will give error responses or time out if an unsupported access is attempted. Typically, platform-specific machine-mode code will extract PMAs and ultimately present this information to higher-level less-privileged software using some standard representation.
Where platforms support dynamic reconfiguration of PMAs, an interface will be provided to set the attributes by passing requests to a machine-mode driver that can correctly reconfigure the platform. For example, switching cacheability attributes on some memory regions might involve platform-specific operations, such as cache flushes, that are available only to machine-mode.
3.5.1 Main Memory versus I/O versus Empty Regions
The most important characterization of a given memory address range is whether it holds regular main memory, or I/O devices, or is empty. Regular main memory is required to have a number of properties, specified below, whereas I/O devices can have a much broader range of attributes. Memory regions that do not fit into regular main memory, for example, device scratchpad RAMs, are categorized as I/O regions. Empty regions are also classified as I/O regions but with attributes specifying that no accesses are supported.
3.5.2 Supported Access Type PMAs
Access types specify which access widths, from 8-bit byte to long multi-word burst, are supported, and also whether misaligned accesses are supported for each access width.
Although software running on a RISC-V hart cannot directly generate bursts to memory, software might have to program DMA engines to access I/O devices and might therefore need to know which access sizes are supported.
Main memory regions always support read, write, and execute of all access widths required by the attached devices.
In some cases, the design of a processor or device accessing main memory might support other widths, but must be able to function with the types supported by the main memory.
I/O regions can specify which combinations of read, write, or execute accesses to which data widths are supported.
3.5.3 Atomicity PMAs
Atomicity PMAs describes which atomic instructions are supported in this address region. Main memory regions must support the atomic operations required by the processors attached. I/O regions may only support a subset or none of the processor-supported atomic operations.
Support for atomic instructions is divided into two categories:
LR/SC and AMOs. Within AMOs, there are four levels of
support: AMONone, AMOSwap, AMOLogical, and
AMOArithmetic. AMONone indicates that no AMO operations are
supported. AMOSwap indicates that only amoswap instructions are
supported in this address range. AMOLogical indicates that swap
instructions plus all the logical AMOs (amoand, amoor,
amoxor) are supported. AMOArithmetic indicates that all RISC-V
AMOs are supported. For each level of support, naturally aligned AMOs
of a given width are supported if the underlying memory region
supports reads and writes of that width.
| AMO Class | Supported Operations |
|---|---|
| AMONone | None |
| AMOSwap | amoswap |
| AMOLogical | above + amoand, amoor, amoxor |
| AMOArithmetic | above + amoadd, amomin, amomax, amominu, amomaxu |
We recommend providing at least AMOLogical support for I/O regions where possible. Most I/O regions will not support LR/SC accesses, as these are most conveniently built on top of a cache-coherence scheme.
3.5.4 Memory-Ordering PMAs
Regions of the address space are classified as either main memory or I/O for the purposes of ordering by the FENCE instruction and atomic-instruction ordering bits.
Accesses by one hart to main memory regions are observable not only by other harts but also by other devices with the capability to initiate requests in the main memory system (e.g., DMA engines). Main memory regions always have the standard RISC-V relaxed memory model.
Accesses by one hart to the I/O space are observable not only by other harts and bus mastering devices, but also by targeted slave I/O devices. Within I/O, regions may further be classified as implementing either relaxed or strong ordering. A relaxed I/O region has no ordering guarantees on how memory accesses made by one hart are observable by different harts or I/O devices beyond those enforced by FENCE and AMO instructions. A strongly ordered I/O region ensures that all accesses made by a hart to that region are only observable in program order by all other harts or I/O devices.
Each strongly ordered I/O region specifies a numbered ordering channel, which is a mechanism by which ordering guarantees can be provided between different I/O regions. Channel 0 is used to indicate point-to-point strong ordering only, where only accesses by the hart to the single associated I/O region are strongly ordered.
Channel 1 is used to provide global strong ordering across all I/O
regions. Any accesses by a hart to any I/O region associated with
channel 1 can only be observed to have occurred in program order by all
other harts and I/O devices, including relative to accesses made by
that hart to relaxed I/O regions or strongly ordered I/O regions with
different channel numbers. In other words, any access to a region in
channel 1 is equivalent to executing a fence io,io
instruction before and after the instruction.
Other larger channel numbers provide program ordering to accesses by that hart across any regions with the same channel number.
Systems might support dynamic configuration of ordering properties on each memory region.
Strong ordering can be used to improve compatibility with legacy device driver code, or to enable increased performance compared to insertion of explicit ordering instructions when the implementation is known to not reorder accesses.
Local strong ordering (channel 0) is the default form of strong ordering as it is often straightforward to provide if there is only a single in-order communication path between the hart and the I/O device.
Generally, different strongly ordered I/O regions can share the same ordering channel without additional ordering hardware if they share the same interconnect path and the path does not reorder requests.
3.5.5 Coherence and Cacheability PMAs
Coherence is a property defined for a single physical address, and indicates that writes to that address by one agent will eventually be made visible to other agents in the system. Coherence is not to be confused with the memory consistency model of a system, which defines what values a memory read can return given the previous history of reads and writes to the entire memory system. In RISC-V platforms, the use of hardware-incoherent regions is discouraged due to software complexity, performance, and energy impacts.
The cacheability of a memory region should not affect the software view of the region except for differences reflected in other PMAs, such as main memory versus I/O classification, memory ordering, supported accesses and atomic operations, and coherence. For this reason, we treat cacheability as a platform-level setting managed by machine-mode software only.
Where a platform supports configurable cacheability settings for a memory region, a platform-specific machine-mode routine will change the settings and flush caches if necessary, so the system is only incoherent during the transition between cacheability settings. This transitory state should not be visible to lower privilege levels.
We categorize RISC-V caches into three types: master-private, shared, and slave-private. Master-private caches are attached to a single master agent, i.e., one that issues read/write requests to the memory system. Shared caches are located inbetween masters and slaves and may be hierarchically organized. Slave-private caches do not impact coherence, as they are local to a single slave and do not affect other PMAs at a master, so are not considered further here. We use private cache to mean a master-private cache in the following section, unless explicitly stated otherwise.
Coherence is straightforward to provide for a shared memory region that is not cached by any agent. The PMA for such a region would simply indicate it should not be cached in a private or shared cache.
Coherence is also straightforward for read-only regions, which can be safely cached by multiple agents without requiring a cache-coherence scheme. The PMA for this region would indicate that it can be cached, but that writes are not supported.
Some read-write regions might only be accessed by a single agent, in which case they can be cached privately by that agent without requiring a coherence scheme. The PMA for such regions would indicate they can be cached. The data can also be cached in a shared cache, as other agents should not access the region.
If an agent can cache a read-write region that is accessible by other agents, whether caching or non-caching, a cache-coherence scheme is required to avoid use of stale values. In regions lacking hardware cache coherence (hardware-incoherent regions), cache coherence can be implemented entirely in software, but software coherence schemes are notoriously difficult to implement correctly and often have severe performance impacts due to the need for conservative software-directed cache-flushing. Hardware cache-coherence schemes require more complex hardware and can impact performance due to the cache-coherence probes, but are otherwise invisible to software.
For each hardware cache-coherent region, the PMA would indicate that the region is coherent and which hardware coherence controller to use if the system has multiple coherence controllers. For some systems, the coherence controller might be an outer-level shared cache, which might itself access further outer-level cache-coherence controllers hierarchically.
Most memory regions within a platform will be coherent to software, because they will be fixed as either uncached, read-only, hardware cache-coherent, or only accessed by one agent.
3.5.6 Idempotency PMAs
Idempotency PMAs describe whether reads and writes to an address region are idempotent. Main memory regions are assumed to be idempotent. For I/O regions, idempotency on reads and writes can be specified separately (e.g., reads are idempotent but writes are not). If accesses are non-idempotent, i.e., there is potentially a side effect on any read or write access, then speculative or redundant accesses must be avoided.
For the purposes of defining the idempotency PMAs, changes in observed memory ordering created by redundant accesses are not considered a side effect.
While hardware should always be designed to avoid speculative or redundant accesses to memory regions marked as non-idempotent, it is also necessary to ensure software or compiler optimizations do not generate spurious accesses to non-idempotent memory regions.
Non-idempotent regions might not support misaligned accesses, in which case software might emulate misaligned accesses as a sequence of aligned accesses, each possibly causing side effects. Therefore, portable software should not issue misaligned accesses to non-idempotent regions.
3.6 Physical Memory Protection
To support secure processing and contain faults, it is desirable to limit the physical addresses accessible by software running on a hart. An optional physical memory protection (PMP) unit provides per-hart machine-mode control registers to allow physical memory access privileges (read, write, execute) to be specified for each physical memory region. The PMP values are checked in parallel with the PMA checks described in Section 1.5.
The granularity of PMP access control settings are platform-specific and within a platform may vary by physical memory region, but the standard PMP encoding supports regions as small as four bytes. Certain regions’ privileges can be hardwired—for example, some regions might only ever be visible in machine mode but in no lower-privilege layers.
Platforms vary widely in demands for physical memory protection, and some platforms may provide other PMP structures in addition to or instead of the scheme described in this section.
PMP checks are applied to all accesses when the hart is running in
S or U modes, and for loads and stores when the MPRV bit is set in
the mstatus register and the MPP field in the mstatus
register contains S or U. PMP checks are also applied to page-table
accesses for virtual-address translation, for which the effective
privilege mode is S. Optionally, PMP checks may additionally apply
to M-mode accesses, in which case the PMP registers themselves are
locked, so that even M-mode software cannot change them without
a system reset. In effect, PMP can grant permissions to S and U
modes, which by default have none, and can revoke permissions
from M-mode, which by default has full permissions.
PMP violations are always trapped precisely at the processor.
3.6.1 Physical Memory Protection CSRs
PMP entries are described by an 8-bit configuration register and one XLEN-bit address register. Some PMP settings additionally use the address register associated with the preceding PMP entry. Up to 16 PMP entries are supported. If any PMP entries are implemented, then all PMP CSRs must be implemented, but all PMP CSR fields are WARL and may be hardwired to zero. PMP CSRs are only accessible to M-mode.
The PMP configuration registers are densely packed into CSRs to minimize
context-switch time. For RV32, four CSRs, pmpcfg0–pmpcfg3, hold
the configurations pmp0cfg–pmp15cfg for the 16 PMP entries, as
shown in Figure 1.20. For RV64, pmpcfg0 and pmpcfg2
hold the configurations for the 16 PMP entries, as shown in
Figure 1.21; pmpcfg1 and pmpcfg3 are illegal.
RV64 systems use pmpcfg2, rather than pmpcfg1, to hold
configurations for PMP entries 8–15. This design reduces the cost of
supporting multiple M-XLEN values, since the configurations for PMP
entries 8–11 appear in pmpcfg2[31:0] for both RV32 and RV64.
The PMP address registers are CSRs named pmpaddr0–pmpaddr15.
Each PMP address register encodes bits 33–2 of a 34-bit physical address for
RV32, as shown in Figure 1.22. For RV64, each PMP address
register encodes bits 55–2 of a 56-bit physical address, as shown in
Figure 1.23. Not all physical address bits may be implemented,
and so the pmpaddr registers are WARL.
The Sv32 page-based virtual-memory scheme described in Section [sec:sv32] supports 34-bit physical addresses for RV32, so the PMP scheme must support addresses wider than XLEN for RV32. The Sv39 and Sv48 page-based virtual-memory schemes described in Sections [sec:sv39] and [sec:sv48] support a 56-bit physical address space, so the RV64 PMP address registers impose the same limit.
Figure 1.24 shows the layout of a PMP configuration register. The R, W, and X bits, when set, indicate that the PMP entry permits read, write, and instruction execution, respectively. When one of these bits is clear, the corresponding access type is denied. The remaining two fields, A and L, are described in the following sections.
Address Matching
The A field in a PMP entry’s configuration register encodes the address-matching mode of the associated PMP address register. The encoding of this field is shown in Table [pmpcfg-a]. When A=0, this PMP entry is disabled and matches no addresses. Two other address-matching modes are supported: naturally aligned power-of-2 regions (NAPOT), including the special case of naturally aligned four-byte regions (NA4); and the top boundary of an arbitrary range (TOR). These modes support four-byte granularity.
| A | Name | Description |
|---|---|---|
| 0 | OFF | Null region (disabled) |
| 1 | TOR | Top of range |
| 2 | NA4 | Naturally aligned four-byte region |
| 3 | NAPOT | Naturally aligned power-of-two region, ≥8 bytes |
NAPOT ranges make use of the low-order bits of the associated address register to encode the size of the range, as shown in Table 1.25.
If TOR is selected, the associated address register forms the top of the address range, and the preceding PMP address register forms the bottom of the address range. If PMP entry i’s A field is set to TOR, the entry matches any address a such that ${\tt pmpaddr}_{i-1}\leq a < {\tt pmpaddr}_i$. If PMP entry 0’s A field is set to TOR, zero is used for the lower bound, and so it matches any address $a < {\tt pmpaddr}_0$.
Locking and Privilege Mode
The L bit indicates that the PMP entry is locked, i.e., writes to the
configuration register and associated address registers are ignored. Locked
PMP entries may only be unlocked with a system reset. If PMP entry i is
locked, writes to pmpicfg and pmpaddri are ignored.
Additionally, if pmpicfg.A is set to TOR, writes to pmpaddri-1 are ignored.
In addition to locking the PMP entry, the L bit indicates whether the R/W/X permissions are enforced on M-mode accesses. When the L bit is set, these permissions are enforced for all privilege modes. When the L bit is clear, any M-mode access matching the PMP entry will succeed; the R/W/X permissions apply only to S and U modes.
Priority and Matching Logic
PMP entries are statically prioritized. The lowest-numbered PMP entry that
matches any byte of an access determines whether that access succeeds or
fails. The matching PMP entry must match all bytes of an access, or the
access fails, irrespective of the L, R, W, and X bits. For example, if a PMP
entry is configured to match the four-byte range 0xC–0xF, then an
8-byte access to the range 0x8–0xF will fail, assuming that
PMP entry is the highest-priority entry that matches those addresses.
If a PMP entry matches all bytes of an access, then the L, R, W, and X bits determine whether the access succeeds or fails. If the L bit is clear and the privilege mode of the access is M, the access succeeds. Otherwise, if the L bit is set or the privilege mode of the access is S or U, then the access succeeds only if the R, W, or X bit corresponding to the access type is set.
If no PMP entry matches an M-mode access, the access succeeds. If no PMP entry matches an S-mode or U-mode access, but at least one PMP entry is implemented, the access fails.
Failed accesses generate a load, store, or instruction access exception. Note that a single instruction may generate multiple accesses, which may not be mutually atomic. An access exception is generated if at least one access generated by an instruction fails, though other accesses generated by that instruction may succeed with visible side effects. Notably, instructions that reference virtual memory are decomposed into multiple accesses.
On some implementations, misaligned loads, stores, and instruction fetches may also be decomposed into multiple accesses, some of which may succeed before an access exception occurs. In particular, a portion of a misaligned store that passes the PMP check may become visible, even if another portion fails the PMP check. The same behavior may manifest for floating-point stores wider than XLEN bits (e.g., the FSD instruction in RV32D), even when the store address is naturally aligned.
The base width can be quickly ascertained using branches on the sign of the returned
misavalue, and possibly a shift left by one and a second branch on the sign. These checks can be written in assembly code without knowing the register width (XLEN) of the machine. The base width is given by XLEN = 2MXL + 4.The base width can also be found if
misais zero, by placing the immediate 4 in a register then shifting the register left by 31 bits at a time. If zero after one shift, then the machine is RV32. If zero after two shifts, then the machine is RV64, else RV128.