Five EmbedDev

An Embedded RISC-V Blog

1. Introduction

2. Control and Status Registers (CSRs)

3. Machine-Level ISA, version 1.10

4. Supervisor-Level ISA, Version 1.10

5. Hypervisor Extensions, Version 0.0

6. Machine Configuration Description

7. Platform-Level Interrupt Controller (PLIC)

8. RISC-V Privileged Instruction Set Listings

9. History

The RISC-V Instruction Set Manual, Volume II: Privileged Architecture , riscv-priv-1.10 2017/05/07

5 Hypervisor Extensions, Version 0.0

This chapter is a placeholder for RISC-V hypervisor support with an extended S-mode.

The privileged architecture is designed to simplify the use of classic virtualization techniques, where a guest OS is run at user-level, as the few privileged instructions can be easily detected and trapped.