Five EmbedDev

An Embedded RISC-V Blog

Preface

1. Introduction

2. RV32I Base Integer Instruction Set, Version 2.0

5. RV32E Base Integer Instruction Set, Version 1.9

6. RV64I Base Integer Instruction Set, Version 2.0

7. RV128I Base Integer Instruction Set, Version 1.7

8. M Standard Extension for Integer Multiplication and

9. A Standard Extension for Atomic Instructions, Version 2.0

12. F Standard Extension for Single-Precision Floating-Point,

13. D Standard Extension for Double-Precision Floating-Point,

14. Q Standard Extension for Quad-Precision Floating-Point,

17. C Standard Extension for Compressed Instructions, Version

18. B Standard Extension for Bit Manipulation, Version 0.0

19. J Standard Extension for Dynamically Translated Languages, Version 0.0

20. P Standard Extension for Packed-SIMD Instructions,

21. V Standard Extension for Vector Operations, Version 0.2

25. RV32/64G Instruction Set Listings

26. Extending RISC-V

27. ISA Subset Naming Conventions

28. History and Acknowledgments

RISC-V Instruction Set Manual, Volume I: RISC-V User-Level ISA , riscv-priv-1.10 2017/05/07

[instr-table]

[instr-table]

[instr-table]

Instruction listing for RISC-V

© RISC-V Foundation, CC BY 4.0. Coverted to HTML from src/instr-table.tex(riscv-priv-1.10) using Pandoc. For the official specifications refer to riscv.org.