1. "Zfa" Standard Extension for Additional FloatingPoint Instructions, Version 1.0
Zfa is frozen. 
This chapter describes the Zfa standard extension, which adds instructions for immediate loads, IEEE 7542019 minimum and maximum operations, roundtointeger operations, and quiet floatingpoint comparisons. For RV32D, the Zfa extension also adds instructions to transfer doubleprecision floatingpoint values to and from integer registers, and for RV64Q, it adds analogous instructions for quadprecision floatingpoint values. The Zfa extension depends on the F extension.
1.1. LoadImmediate Instructions
The FLI.S instruction loads one of 32 singleprecision floatingpoint constants, encoded in the rs1 field, into floatingpoint register rd. The correspondence of rs1 field values and singleprecision floatingpoint values is shown in Table 37. FLI.S is encoded like FMV.W.X, but with rs2=1.
rs1  Value  Sign  Exponent  Significand 

0 
\(1.0\) 



1 
Minimum positive normal 



2 
\(1.0 \times 2^{16}\) 



3 
\(1.0 \times 2^{15}\) 



4 
\(1.0 \times 2^{8}\) 



5 
\(1.0 \times 2^{7}\) 



6 
0.0625 (\(2^{4}\)) 



7 
0.125 (\(2^{3}\)) 



8 
0.25 



9 
0.3125 



10 
0.375 



11 
0.4375 



12 
0.5 



13 
0.625 



14 
0.75 



15 
0.875 



16 
1.0 



17 
1.25 



18 
1.5 



19 
1.75 



20 
2.0 



21 
2.5 



22 
3 



23 
4 



24 
8 



25 
16 



26 
128 (\(2^7\)) 



27 
256 (\(2^8\)) 



28 
\(2^{15}\) 



29 
\(2^{16}\) 



30 
\(+\infty\) 



31 
Canonical NaN 



The preferred assembly syntax for entries 1, 30, and 31 is 
The set of 32 constants was chosen by examining floatingpoint libraries, including the C standard math library, and to optimize fixedpoint to floatingpoint conversion. Entries 822 follow a regular encoding pattern. No entry sets mantissa bits other than the two most significant ones. 
If the D extension is implemented, FLI.D performs the analogous operation, but loads a doubleprecision value into floatingpoint register rd. Note that entry 1 (corresponding to the minimum positive normal value) has a numerically different value for doubleprecision than for singleprecision. FLI.D is encoded like FLI.S, but with fmt=D.
If the Q extension is implemented, FLI.Q performs the analogous operation, but loads a quadprecision value into floatingpoint register rd. Note that entry 1 (corresponding to the minimum positive normal value) has a numerically different value for quadprecision. FLI.Q is encoded like FLI.S, but with fmt=Q.
If the Zfh or Zvfh extension is implemented, FLI.H performs the analogous operation, but loads a halfprecision floatingpoint value into register rd. Note that entry 1 (corresponding to the minimum positive normal value) has a numerically different value for halfprecision. Furthermore, since \(2^{16}\) is not representable in halfprecision floatingpoint, entry 29 in the table instead loads positive infinity—i.e., it is redundant with entry 30. FLI.H is encoded like FLI.S, but with fmt=H.
Additionally, since \(2^{16}\) and \(2^{15}\) are subnormal in halfprecision, entry 1 is numerically greater than entries 2 and 3 for FLI.H. 
The FLI.fmt instructions never set any floatingpoint exception flags.
1.2. Minimum and Maximum Instructions
The FMINM.S and FMAXM.S instructions are defined like the FMIN.S and FMAX.S instructions, except that if either input is NaN, the result is the canonical NaN.
If the D extension is implemented, FMINM.D and FMAXM.D instructions are analogously defined to operate on doubleprecision numbers.
If the Zfh extension is implemented, FMINM.H and FMAXM.H instructions are analogously defined to operate on halfprecision numbers.
If the Q extension is implemented, FMINM.Q and FMAXM.Q instructions are analogously defined to operate on quadprecision numbers.
These instructions are encoded like their FMIN and FMAX counterparts, but with instruction bit 13 set to 1.
These instructions implement the IEEE 7542019 minimum and maximum operations. 
1.3. RoundtoInteger Instructions
The FROUND.S instruction rounds the singleprecision floatingpoint number in floatingpoint register rs1 to an integer, according to the rounding mode specified in the instruction’s rm field. It then writes that integer, represented as a singleprecision floatingpoint number, to floatingpoint register rd. Zero and infinite inputs are copied to rd unmodified. Signaling NaN inputs cause the invalid operation exception flag to be set; no other exception flags are set. FROUND.S is encoded like FCVT.S.D, but with rs2=4.
The FROUNDNX.S instruction is defined similarly, but it also sets the inexact exception flag if the input differs from the rounded result and is not NaN. FROUNDNX.S is encoded like FCVT.S.D, but with rs2=5.
If the D extension is implemented, FROUND.D and FROUNDNX.D instructions are analogously defined to operate on doubleprecision numbers. They are encoded like FCVT.D.S, but with rs2=4 and 5, respectively,
If the Zfh extension is implemented, FROUND.H and FROUNDNX.H instructions are analogously defined to operate on halfprecision numbers. They are encoded like FCVT.H.S, but with rs2=4 and 5, respectively,
If the Q extension is implemented, FROUND.Q and FROUNDNX.Q instructions are analogously defined to operate on quadprecision numbers. They are encoded like FCVT.Q.S, but with rs2=4 and 5, respectively,
The FROUNDNX.fmt instructions implement the IEEE 7542019 roundToIntegralExact operation, and the FROUND.fmt instructions implement the other operations in the roundToIntegral family. 
1.4. Modular ConverttoInteger Instruction
The FCVTMOD.W.D instruction is defined similarly to the FCVT.W.D instruction, with the following differences. FCVTMOD.W.D always rounds towards zero. Bits 31:0 are taken from the rounded, unbounded two’s complement result, then signextended to XLEN bits and written to integer register rd. \(\pm\infty\) and NaN are converted to zero.
Floatingpoint exception flags are raised the same as they would be for FCVT.W.D with the same input operand.
This instruction is only provided if the D extension is implemented. It is encoded like FCVT.W.D, but with the rs2 field set to 8 and the rm field set to 1 (RTZ). Other rm values are reserved.
The assembly syntax requires the RTZ rounding mode to be explicitly
specified, i.e., The FCVTMOD.W.D instruction was added principally to accelerate the processing of JavaScript Numbers. Numbers are doubleprecision values, but some operators implicitly truncate them to signed integers mod \(2^{32}\). 
1.5. Move Instructions
For RV32 only, if the D extension is implemented, the FMVH.X.D instruction moves bits 63:32 of floatingpoint register rs1 into integer register rd. It is encoded in the OPFP major opcode with funct3=0, rs2=1, and funct7=1110001.
FMVH.X.D is used in conjunction with the existing FMV.X.W instruction to move a doubleprecision floatingpoint number to a pair of xregisters. 
For RV32 only, if the D extension is implemented, the FMVP.D.X instruction moves a doubleprecision number from a pair of integer registers into a floatingpoint register. Integer registers rs1 and rs2 supply bits 31:0 and 63:32, respectively; the result is written to floatingpoint register rd. FMVP.D.X is encoded in the OPFP major opcode with funct3=0 and funct7=1011001.
For RV64 only, if the Q extension is implemented, the FMVH.X.Q instruction moves bits 127:64 of floatingpoint register rs1 into integer register rd. It is encoded in the OPFP major opcode with funct3=0, rs2=1, and funct7=1110011.
FMVH.X.Q is used in conjunction with the existing FMV.X.D instruction to move a quadprecision floatingpoint number to a pair of xregisters. 
For RV64 only, if the Q extension is implemented, the FMVP.Q.X instruction moves a doubleprecision number from a pair of integer registers into a floatingpoint register. Integer registers rs1 and rs2 supply bits 63:0 and 127:64, respectively; the result is written to floatingpoint register rd. FMVP.Q.X is encoded in the OPFP major opcode with funct3=0 and funct7=1011011.
1.6. Comparison Instructions
The FLEQ.S and FLTQ.S instructions are defined like the FLE.S and FLT.S instructions, except that quiet NaN inputs do not cause the invalid operation exception flag to be set.
If the D extension is implemented, FLEQ.D and FLTQ.D instructions are analogously defined to operate on doubleprecision numbers.
If the Zfh extension is implemented, FLEQ.H and FLTQ.H instructions are analogously defined to operate on halfprecision numbers.
If the Q extension is implemented, FLEQ.Q and FLTQ.Q instructions are analogously defined to operate on quadprecision numbers.
These instructions are encoded like their FLE and FLT counterparts, but with instruction bit 14 set to 1.
We do not expect analogous comparison instructions will be added to the vector ISA, since they can be reasonably efficiently emulated using masking. 