1. RV64I Base Integer Instruction Set, Version 2.1
This chapter describes the RV64I base integer instruction set, which builds upon the RV32I variant described in [rv32]. This chapter presents only the differences with RV32I, so should be read in conjunction with the earlier chapter.
1.1. Register State
RV64I widens the integer registers and supported user address space to 64 bits (XLEN=64 in [gprs]).
1.2. Integer Computational Instructions
Most integer computational instructions operate on XLENbit values. Additional instruction variants are provided to manipulate 32bit values in RV64I, indicated by a 'W' suffix to the opcode. These "*W" instructions ignore the upper 32 bits of their inputs and always produce 32bit signed values, signextending them to 64 bits, i.e. bits XLEN1 through 31 are equal.
The compiler and calling convention maintain an invariant that all 32bit values are held in a signextended format in 64bit registers. Even 32bit unsigned integers extend bit 31 into bits 63 through 32. Consequently, conversion between unsigned and signed 32bit integers is a noop, as is conversion from a signed 32bit integer to a signed 64bit integer. Existing 64bit wide SLTU and unsigned branch compares still operate correctly on unsigned 32bit integers under this invariant. Similarly, existing 64bit wide logical operations on 32bit signextended integers preserve the signextension property. A few new instructions (ADD[I]W/SUBW/SxxW) are required for addition and shifts to ensure reasonable performance for 32bit values. 
1.2.1. Integer RegisterImmediate Instructions
ADDIW is an RV64I instruction that adds the signextended 12bit immediate to register rs1 and produces the proper signextension of a 32bit result in rd. Overflows are ignored and the result is the low 32 bits of the result signextended to 64 bits. Note, ADDIW rd, rs1, 0 writes the signextension of the lower 32 bits of register rs1 into register rd (assembler pseudoinstruction SEXT.W).
Shifts by a constant are encoded as a specialization of the Itype format using the same instruction opcode as RV32I. The operand to be shifted is in rs1, and the shift amount is encoded in the lower 6 bits of the Iimmediate field for RV64I. The right shift type is encoded in bit 30. SLLI is a logical left shift (zeros are shifted into the lower bits); SRLI is a logical right shift (zeros are shifted into the upper bits); and SRAI is an arithmetic right shift (the original sign bit is copied into the vacated upper bits).
SLLIW, SRLIW, and SRAIW are RV64Ionly instructions that are analogously defined but operate on 32bit values and signextend their 32bit results to 64 bits. SLLIW, SRLIW, and SRAIW encodings with imm[5] ≠ 0 are reserved.
Previously, SLLIW, SRLIW, and SRAIW with imm[5] ≠ 0 were defined to cause illegalinstruction exceptions, whereas now they are marked as reserved. This is a backwardscompatible change. 
LUI (load upper immediate) uses the same opcode as RV32I. LUI places the 32bit Uimmediate into register rd, filling in the lowest 12 bits with zeros. The 32bit result is signextended to 64 bits.
AUIPC (add upper immediate to pc
) uses the same opcode as RV32I. AUIPC
is used to build pc
relative addresses and uses the Utype format.
AUIPC forms a 32bit offset from the Uimmediate, filling in the lowest
12 bits with zeros, signextends the result to 64 bits, adds it to the
address of the AUIPC instruction, then places the result in register
rd.
Note that the set of address offsets that can be formed by pairing LUI with LD, AUIPC with JALR, etc. in RV64I is [\({}2^{31}{}2^{11}\), \(2^{31}{}2^{11}{}1\)]. 
1.2.2. Integer RegisterRegister Operations
ADDW and SUBW are RV64Ionly instructions that are defined analogously to ADD and SUB but operate on 32bit values and produce signed 32bit results. Overflows are ignored, and the low 32bits of the result is signextended to 64bits and written to the destination register.
SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value in register rs1 by the shift amount held in register rs2. In RV64I, only the low 6 bits of rs2 are considered for the shift amount.
SLLW, SRLW, and SRAW are RV64Ionly instructions that are analogously defined but operate on 32bit values and signextend their 32bit results to 64 bits. The shift amount is given by rs2[4:0].
1.3. Load and Store Instructions
RV64I extends the address space to 64 bits. The execution environment will define what portions of the address space are legal to access.
The LD instruction loads a 64bit value from memory into register rd for RV64I.
The LW instruction loads a 32bit value from memory and signextends this to 64 bits before storing it in register rd for RV64I. The LWU instruction, on the other hand, zeroextends the 32bit value from memory for RV64I. LH and LHU are defined analogously for 16bit values, as are LB and LBU for 8bit values. The SD, SW, SH, and SB instructions store 64bit, 32bit, 16bit, and 8bit values from the low bits of register rs2 to memory respectively.
1.4. HINT Instructions
All instructions that are microarchitectural HINTs in RV32I (see [rv32]) are also HINTs in RV64I. The additional computational instructions in RV64I expand both the standard and custom HINT encoding spaces.
Table 1 lists all RV64I HINT code points. 91% of the HINT space is reserved for standard HINTs, but none are presently defined. The remainder of the HINT space is designated for custom HINTs; no standard HINTs will ever be defined in this subspace.
Instruction  Constraints  Code Points  Purpose 

LUI 
rd=x0 
\(2^{20}\) 
Designated for future standard use 
AUIPC 
rd=x0 
\(2^{20}\) 

ADDI 
rd=x0, and either rs1≠x0 or imm≠0 
\(2^{17}1\) 

ANDI 
rd=x0 
\(2^{17}\) 

ORI 
rd=x0 
\(2^{17}\) 

XORI 
rd=x0 
\(2^{17}\) 

ADDIW 
rd=x0 
\(2^{17}\) 

ADD 
rd=x0, rs1≠x0 
\(2^{10}32\) 

ADD 
rd=x0, rs1=x0, rs2≠x2x5 
28 

ADD 
rd=x0, rs1=x0, rs2=x2x5 
4 
(rs2=x2) NTL.P1 
SUB 
rd=x0 
\(2^{10}\) 
Designated for future standard use 
AND 
rd=x0 
\(2^{10}\) 

OR 
rd=x0 
\(2^{10}\) 

XOR 
rd=x0 
\(2^{10}\) 

SLL 
rd=x0 
\(2^{10}\) 

SRL 
rd=x0 
\(2^{10}\) 

SRA 
rd=x0 
\(2^{10}\) 

ADDW 
rd=x0 
\(2^{10}\) 

SUBW 
rd=x0 
\(2^{10}\) 

SLLW 
rd=x0 
\(2^{10}\) 

SRLW 
rd=x0 
\(2^{10}\) 

SRAW 
rd=x0 
\(2^{10}\) 

FENCE 
rd=x0, rs1≠x0,fm=0, and either pred=0 or succ=0 
\(2^{10}63\) 

FENCE 
rd≠x0, rs1=x0, fm=0, and either pred=0 or succ=0 
\(2^{10}63\) 

FENCE 
rd=rs1=x0, fm=0, pred=0, succ≠0 
15 

FENCE 
pred=0 or succ=0, pred≠W, succ =0 
15 

FENCE 
rd=rs1=x0, fm=0, pred=W, succ=0 
1 
PAUSE 
SLTI 
rd=x0 
\(2^{17}\) 
Designated for custom use 
SLTIU 
rd=x0 
\(2^{17}\) 

SLLI 
rd=x0 
\(2^{11}\) 

SRLI 
rd=x0 
\(2^{11}\) 

SRAI 
rd=x0 
\(2^{11}\) 

SLLIW 
rd=x0 
\(2^{10}\) 

SRLIW 
rd=x0 
\(2^{10}\) 

SRAIW 
rd=x0 
\(2^{10}\) 

SLT 
rd=x0 
\(2^{10}\) 

SLTU 
rd=x0 
\(2^{10}\) 