Five EmbedDev

An Embedded RISC-V Blog

1. Introduction

1. RV32I Base Integer Instruction Set, Version 2.1

1. RV32E and RV64E Base Integer Instruction Sets, Version 2.0

1. RV64I Base Integer Instruction Set, Version 2.1

1. RV128I Base Integer Instruction Set, Version 1.7

1. RVWMO Memory Consistency Model, Version 2.0

1. RV32/64G Instruction Set Listings

1. Extending RISC-V

1. ISA Extension Naming Conventions

1. History and Acknowledgments

Appendix A: RVWMO Explanatory Material, Version 0.1

Appendix A: Formal Memory Model Specifications, Version 0.1

Index

Bibliography

RISC-V Instruction Set Manual, Volume I: RISC-V User-Level ISA , riscv-isa-release-1239329-2023-05-23-96-g1ee25e1 2023/09/27

1. "V" Standard Extension for Vector Operations, Version 1.0

The specification is currently hosted at https://github.com/riscv/riscv-v-spec.

The base vector extension is intended to provide general support for data-parallel execution within the 32-bit instruction encoding space, with later vector extensions supporting richer functionality for certain domains.

© RISC-V Foundation, CC BY 4.0. Coverted to HTML from src/v-st-ext.adoc(riscv-isa-release-1239329-2023-05-23-96-g1ee25e1) using Pandoc. For the official specifications refer to riscv.org.