Five EmbedDev

An Embedded RISC-V Blog

1. Introduction

1. RV32I Base Integer Instruction Set, Version 2.1

1. RV32E and RV64E Base Integer Instruction Sets, Version 2.0

1. RV64I Base Integer Instruction Set, Version 2.1

1. RV128I Base Integer Instruction Set, Version 1.7

1. RVWMO Memory Consistency Model, Version 2.0

1. RV32/64G Instruction Set Listings

1. Extending RISC-V

1. ISA Extension Naming Conventions

1. History and Acknowledgments

Appendix A: RVWMO Explanatory Material, Version 0.1

Appendix A: Formal Memory Model Specifications, Version 0.1

Index

Bibliography

RISC-V Instruction Set Manual, Volume I: RISC-V User-Level ISA , riscv-isa-release-1239329-2023-05-23-96-g1ee25e1 2023/09/27

1. "P" Standard Extension for Packed-SIMD Instructions, Version 0.2

Discussions at the 5th RISC-V workshop indicated a desire to drop this packed-SIMD proposal for floating-point registers in favor of standardizing on the V extension for large floating-point SIMD operations. However, there was interest in packed-SIMD fixed-point operations for use in the integer registers of small RISC-V implementations. A task group is working to define the new P extension.