The User ISA and Privileged ISA have been updated to tag draft-20191228-a6c204f in the upstream repo and re-generated as HTML.

The upstream changelog from git is:

• Fix FENCE.I cross-reference
• FENCE.I isn’t in the I base
• Rephrase awkward sentence
• Clarify that access exceptions on jump targets are reported on the target
• Bump version number 20191214-draft
• A extension v2.1 has been ratified
• multiplicand, not multiplier, is signed
• Forgot to include frm as PPO source for FCVT.L[U].S/FCVT.S.L[U]
• Add pass-through interrupt support and hgeie/hgeip registers
• Update preface
• MRET and SRET clear MPRV when leaving M-mode
• “two-level translation” -> “two-stage translation”
• Add note about negative htimedelta values
• tweak
• satp.PPN’s WARLness is separate from physical address validity
• Reserve satp fields when MODE=Bare
• Hypervisor tweaks
• Convert samepage-commentary blocks to commentary blocks
• Improve commentary environment page-break behavior
• hypervisor draft v0.5
• Merge branch ‘pdonahue-ventana-unspecified’
• clarify that extra PTE bits are reserved for standard use
• Describe what we mean by endianness
• Explicitly remark that SUM/MXR changes don’t need an SFENCE.VMA
• fix formatting
• Incorporate feedback from Paul Donahue
• Incorporate Anthony Coulter’s feedback
• Address some of Derek’s feedback
• Fix editing error that allowed FENCE.I in LR/SC sequences
• Fix typo
• Incorporate aspects of PR #444
• Add a description of the reservability PMA.
• Use effective address consistently
• Avoid using “virtual address” in normative text of unprivileged spec (#430)
• Incorporate some of #416 and #418
• More LR/SC feedback
• Move CAS code figure to the same page it’s referenced on
• Introduce “reservation set” terminology
• More Derek feedback
• Address Derek’s feedback
• Constrained loops must use same virtual address for SC
• Clarify that LR/SC reservation granule mustn’t cross page boundaries
• Incorporate Dan’s feedback
• More LR/SC updates
• Remove page breaks
• Weaken LR/SC progress guarantee
• Clarify that pmpcfg.L takes effect even when pmpcfg.A=0
• Improve supervisor interrupt control section
• Fix editing error in Atomicity PMA figure caption
• Update preface
• Improve interrupt-delegation description
• Add mcause section label
• Permit hardwiring of some mideleg bits to 1
• Refine xepc/xtval WARL requirements
• Make PMP description consistent with MPRV description
• Mark misa.G as reserved until the discovery mechansim is defined
• marchid for c-class core of SHAKTI (#448)
• Remove outdated commentary
• mstatus TVM, TW, and TSR are WARL fields
• Fix outcome description for Figure A.15
• Closes #359.
• Like page-table walks, main memory might not support i-fetch
• Main memory support atomics is a platform mandate, not an ISA one
• scause must be able to hold the values 0-31
• Page-table walks are distinct access types for PMA purposes
• Update contributors
• Remove released PDFs
• Add link to archive
• Relaxed I/O adheres to Appendix A 4.2
• Merge pull request #441 from Columbus240/I440
• Define Upper-Half User-Level Timer CSRs for RV32I (#439)