Five EmbedDev logo Five EmbedDev

An Embedded RISC-V Blog
RISC-V Instruction Set Manual, Volume I: RISC-V User-Level ISA , IMFDQC-Ratification-20190305 2019/03/05

The RISC-V Instruction Set Manual


Volume I: Unprivileged ISA
Document Version 20190305-Base-Ratification

Editors: Andrew Waterman1, Krste Asanović1, 2
1SiFive Inc.,
2CS Division, EECS Department, University of California, Berkeley
andrew@sifive.com, krste@berkeley.edu

Contributors to all versions of the spec in alphabetical order (please contact editors to suggest corrections): Arvind, Krste Asanović, Rimas Avižienis, Jacob Bachmeyer, Christopher F. Batten, Allen J. Baum, Alex Bradbury, Scott Beamer, Preston Briggs, Christopher Celio, Chuanhua Chang, David Chisnall, Paul Clayton, Palmer Dabbelt, Roger Espasa, Shaked Flur, Stefan Freudenberger, Jan Gray, Michael Hamburg, John Hauser, David Horner, Bruce Hoult, Alexandre Joannou, Olof Johansson, Ben Keller, Yunsup Lee, Paul Loewenstein, Daniel Lustig, Yatin Manerkar, Luc Maranget, Margaret Martonosi, Joseph Myers, Vijayanand Nagarajan, Rishiyur Nikhil, Jonas Oberhauser, Stefan O’Rear, Albert Ou, John Ousterhout, David Patterson, Christopher Pulte, Jose Renau, Colin Schmidt, Peter Sewell, Susmit Sarkar, Michael Taylor, Wesley Terpstra, Matt Thomas, Tommy Thorn, Caroline Trippel, Ray VanDeWalker, Muralidaran Vijayaraghavan, Megan Wachs, Andrew Waterman, Robert Watson, Derek Williams, Andrew Wright, Reinoud Zandijk, and Sizhuo Zhang.

This document is released under a Creative Commons Attribution 4.0 International License.

This document is a derivative of “The RISC-V Instruction Set Manual, Volume I: User-Level ISA Version 2.1” released under the following license: © 2010–2017 Andrew Waterman, Yunsup Lee, David Patterson, Krste Asanović. Creative Commons Attribution 4.0 International License.

Please cite as: “The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 20190305-Base-Ratification”, Editors Andrew Waterman and Krste Asanović, RISC-V Foundation, March 2019.

Volume I: RISC-V Unprivileged ISA V20190305-Base-Ratification

[preface]

[intro] [rv32] [zifencei] [rv32e] [rv64] [rv128] [m] [a] [csr] [counters] [f] [d] [q] [rvwmo] [l] [c] [b] [j] [t] [p] [v] [n] [zam] [ztso] [gmaps] [assembly] [extensions] [naming] [history]

[memory]