22 “N” Standard Extension for User-Level Interrupts, Version 1.1
This chapter presents a proposal for adding RISC-V user-level interrupt and exception handling. When the N extension is present, and the outer execution environment has delegated designated interrupts and exceptions to user-level, then hardware can transfer control directly to a user-level trap handler without invoking the outer execution environment.
22.1 Additional CSRs
22.1.1 User Status Register (
ustatus register is a UXLEN-bit read/write register
formatted as shown in Figure 1.1. The
register keeps track of and controls the hart’s current operating
The user interrupt-enable bit UIE disables user-level interrupts when clear. The value of UIE is copied into UPIE when a user-level trap is taken, and the value of UIE is set to zero to provide atomicity for the user-level trap handler.
The UIE and UPIE bits are mirrored in the
registers in the same bit positions.
A new instruction, URET, is used to return from traps in U-mode.
URET copies UPIE into UIE, then sets UPIE, before copying
22.1.2 User Interrupt Registers (
uip register is a UXLEN-bit read/write register containing
information on pending interrupts, while
uie is the corresponding
UXLEN-bit read/write register containing interrupt enable bits.
Three types of interrupts are defined: software interrupts, timer interrupts,
and external interrupts. A user-level software interrupt is triggered
on the current hart by writing 1 to its user software interrupt-pending
(USIP) bit in the
uip register. A pending user-level software
interrupt can be cleared by writing 0 to the USIP bit in
User-level software interrupts are disabled when the USIE bit in the
uie register is clear.
The ABI should provide a mechanism to send interprocessor interrupts to other
harts, which will ultimately cause the USIP bit to be set in the recipient
All bits besides USIP in the
uip register are read-only.
A user-level timer interrupt is pending if the UTIP bit in the
register is set. User-level timer interrupts are disabled when the UTIE
bit in the
uie register is clear. The ABI should provide a
mechanism to clear a pending timer interrupt.
A user-level external interrupt is pending if the UEIP bit in the
uip register is set. User-level external interrupts are disabled
when the UEIE bit in the
uie register is clear. The ABI
should provide facilities to mask, unmask, and query the cause of external
uie registers are subsets of the
Reading any field, or writing any writable field, of
effects a read or write of the homonymous field of
If S-mode is implemented, the
uie registers are also
subsets of the
22.1.3 Machine Trap Delegation Registers (
In systems with the N extension, the
registers, described in Chapter [machine], must be implemented.
In systems that implement S-mode,
behave as described in Chapter [machine].
In systems with only M and U privilege modes, setting a bit in
mideleg delegates the corresponding trap in U-mode to the U-mode trap
22.1.4 Supervisor Trap Delegation Registers (
For systems with both S-mode and the N extension, new CSRs
sideleg are added.
These registers have the same layout as the machine trap delegation registers,
sideleg allow S-mode to delegate traps to U-mode.
Only bits corresponding to traps that have been delegated to S-mode are
writable; the others are hardwired to zero.
Setting a bit in
sideleg delegates the corresponding
trap in U-mode to the U-mode trap handler.
22.1.5 Other CSRs
CSRs are defined analogously to the
22.2 N Extension Instructions
The URET instruction is added to perform the analogous function to MRET and SRET.
22.3 Reducing Context-Swap Overhead
The user-level interrupt-handling registers add considerable state to
the user-level context, yet will usually rarely be active in normal
use. In particular,
only valid during execution of a trap handler.
An NS field can be added to
the format of the FS and XS fields to reduce context-switch overhead
when the values are not live. Execution of URET will place the
utval back into initial state.