Five EmbedDev logo Five EmbedDev

An Embedded RISC-V Blog
RISC-V Instruction Set Manual, Volume I: RISC-V User-Level ISA , 20191214- December 2019

26 RISC-V Assembly Programmer’s Handbook

This chapter is a placeholder for an assembly programmer’s manual.

Table [regmap] lists the assembler mnemonics for the x and f registers and their role in the first standard calling convention.

Register ABI Name Description Saver
x0 zero Hard-wired zero
x1 ra Return address Caller
x2 sp Stack pointer Callee
x3 gp Global pointer
x4 tp Thread pointer
x5 t0 Temporary/alternate link register Caller
x67 t12 Temporaries Caller
x8 s0/fp Saved register/frame pointer Callee
x9 s1 Saved register Callee
x1011 a01 Function arguments/return values Caller
x1217 a27 Function arguments Caller
x1827 s211 Saved registers Callee
x2831 t36 Temporaries Caller
f07 ft07 FP temporaries Caller
f89 fs01 FP saved registers Callee
f1011 fa01 FP arguments/return values Caller
f1217 fa27 FP arguments Caller
f1827 fs211 FP saved registers Callee
f2831 ft811 FP temporaries Caller

There may be future different calling conventions, but note that registers x1, x2, and x5 have special meanings encoded in the standard ISA and/or the compressed extension.

Tables 1.1 and [csr-pseudos] contain a listing of standard RISC-V pseudoinstructions.

RISC-V pseudoinstructions.
pseudoinstruction Base Instruction Meaning
j offset jal x0, offset Jump
jal offset jal x1, offset Jump and link
jr rs jalr x0, 0(rs) Jump register
jalr rs jalr x1, 0(rs) Jump and link register
ret jalr x0, 0(x1) Return from subroutine
call offset auipc x1, {\tt offset[31:12]} + {\tt offset[11]} Call far-away subroutine
jalr x1, offset[11:0](x1)
tail offset auipc x6, {\tt offset[31:12]} + {\tt offset[11]} Tail call far-away subroutine
jalr x0, offset[11:0](x6)
fence fence iorw, iorw Fence on all memory and I/O
rdinstret[h] rd csrrs rd, instret[h], x0 Read instructions-retired counter
rdcycle[h] rd csrrs rd, cycle[h], x0 Read cycle counter
rdtime[h] rd csrrs rd, time[h], x0 Read real-time clock
csrr rd, csr csrrs rd, csr, x0 Read CSR
csrw csr, rs csrrw x0, csr, rs Write CSR
csrs csr, rs csrrs x0, csr, rs Set bits in CSR
csrc csr, rs csrrc x0, csr, rs Clear bits in CSR
csrwi csr, imm csrrwi x0, csr, imm Write CSR, immediate
csrsi csr, imm csrrsi x0, csr, imm Set bits in CSR, immediate
csrci csr, imm csrrci x0, csr, imm Clear bits in CSR, immediate
frcsr rd csrrs rd, fcsr, x0 Read FP control/status register
fscsr rd, rs csrrw rd, fcsr, rs Swap FP control/status register
fscsr rs csrrw x0, fcsr, rs Write FP control/status register
frrm rd csrrs rd, frm, x0 Read FP rounding mode
fsrm rd, rs csrrw rd, frm, rs Swap FP rounding mode
fsrm rs csrrw x0, frm, rs Write FP rounding mode
frflags rd csrrs rd, fflags, x0 Read FP exception flags
fsflags rd, rs csrrw rd, fflags, rs Swap FP exception flags
fsflags rs csrrw x0, fflags, rs Write FP exception flags