8 JTAG Debug Transport Module
This Debug Transport Module is based around a normal JTAG Test Access Port (TAP). The JTAG TAP allows access to arbitrary JTAG registers by first selecting one using the JTAG instruction register (IR), and then accessing it through the JTAG data register (DR).
8.1 JTAG Background
JTAG refers to IEEE Std 1149.1-2013. It is a standard that defines test logic that can be included in an integrated circuit to test the interconnections between integrated circuits, test the integrated circuit itself, and observe or modify circuit activity during the component’s normal operation. This specification uses the latter functionality. The JTAG standard defines a Test Access Port (TAP) that can be used to read and write a few custom registers, which can be used to communicate with debug hardware in a component.
8.2 JTAG DTM Registers
JTAG TAPs used as a DTM must have an IR of at least 5 bits. When the TAP is reset, IR must default to 00001, selecting the IDCODE instruction. A full list of JTAG registers along with their encoding is in Table [dtmTable:jtagregisters]. If the IR actually has more than 5 bits, then the encodings in Table [dtmTable:jtagregisters] should be extended with 0’s in their most significant bits, except for the 0x1f encoding of BYPASS, which must be extended with 1’s in the most significant bits. The only regular JTAG registers a debugger might use are BYPASS and IDCODE, but this specification leaves IR space for many other standard JTAG instructions. Unimplemented instructions must select the BYPASS register.
8.3 Recommended JTAG Connector
To make it easy to acquire debug hardware, this spec recommends a connector that is compatible with the MIPI-10 .05 inch connector specification, as described in the MIPI Alliance Recommendation for Debug and Trace Connectors, Version 1.10.00, 16 March 2011.
The connector has .05 inch spacing, gold-plated male header with .016 inch thick hardened copper or beryllium bronze square posts (SAMTEC FTSH or equivalent). Female connectors are compatible 20μm gold connectors.
Viewing the male header from above (the pins pointing at your eye), a target’s connector looks as it does in Table [tab:mipiten]. The function of each pin is described in Table [tab:pinout].
| VREF DEBUG | 1 | 2 | TMS |
|---|---|---|---|
| GND | 3 | 4 | TCK |
| GND | 5 | 6 | TDO |
| GND or KEY | 7 | 8 | TDI |
| GND | 9 | 10 | nRESET |
If a platform requires nTRST then it is permissible to reuse the nRESET pin as the nTRST signal. If a platform requires both system reset and TAP reset, the MIPI-20 connector should be used. Its physical connector is virtually identical to MIPI-10, except that it’s twice as long, supporting twice as many pins. Its connector is show in Table [tab:mipitwenty].
| VREF DEBUG | 1 | 2 | TMS |
|---|---|---|---|
| GND | 3 | 4 | TCK |
| GND | 5 | 6 | TDO |
| GND or KEY | 7 | 8 | TDI |
| GND | 9 | 10 | nRESET |
| GND | 11 | 12 | RTCK |
| GND | 13 | 14 | nTRST_PD |
| GND | 15 | 16 | nTRST |
| GND | 17 | 18 | DBGRQ |
| GND | 19 | 20 | DBGACK |
|r|c|L|
1 & VREF DEBUG & Reference voltage for logic high.
2 & TMS & JTAG TMS signal, driven by the debug adapter.
4 & TCK & JTAG TCK signal, driven by the debug adapter.
6 & TDO & JTAG TDO signal, driven by the target.
7 & GND or KEY &
This pin may be cut on the male and plugged on the female header to
ensure the header is always plugged in correctly. It is, however,
recommended to use this pin as an additional ground, to allow for
fastest TCK speeds. A shrouded connector should be used to prevent the
cable from being plugged in incorrectly.
8 & TDI & JTAG TDI signal, driven by the debug adapter.
10 & nRESET & Active-low reset signal, driven by the debug adapter.
Asserting reset should reset any RISC-V cores as well as any other
peripherals on the PCB. It should not reset the debug logic. This pin
is optional but strongly encouraged.
If necessary, this pin could be used as nTRST instead.
nRESET should never be connected to the TAP reset, otherwise the
debugger might not be able to debug through a reset to discover the
cause of a crash or to maintain execution control after the reset.
12 & RTCK & Return test clock, driven by the target. A target may relay
the TCK signal here once it has processed it, allowing a debugger to
adjust its TCK frequency in response.
14 & nTRST_PD & Test reset pull-down (optional), driven by the debug
adapter. Same function as nTRST, but with pull-down resistor on target.
16 & nTRST & Test reset (optional), driven by the debug adapter. Used to
reset the JTAG TAP Controller.
18 & TRIGIN & Not used, driven low by the debug adapter.
20 & TRIGOUT & Not used, driven by the target.
The same connectors can be used for 2-wire cJTAG. In that case TMS is used for TMSC, and TCK is used for TCKC.